bit_length is 1 more than needed: subtract 1 from XLEN first

[soc.git] / src / soc / fu / shift_rot / main_stage.py

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index df8b17c23eacd2f62d9696ac37b1c83ca9104edf..4f83a99d91c445fe92b56524b7d98cb7eb8583ba 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -49,7 +49,7 @@ class ShiftRotMainStage(PipeModBase):
             comb += bitwise_lut.inputs[1].eq(self.i.ra)
             comb += bitwise_lut.inputs[2].eq(self.i.rc)
             # 6 == log2(64) because we have 64-bit values
-            grev = GRev(log2_width=XLEN.bit_length())
+            grev = GRev(log2_width=(XLEN-1).bit_length())
             m.submodules.grev = grev
             with m.If(op.is_32bit):
                 # 32-bit, so input is lower 32-bits zero-extended