missing invert_in field from shiftrot input record

[soc.git] / src / soc / fu / shift_rot / main_stage.py

diff --git a/src/soc/fu/shift_rot/main_stage.py b/src/soc/fu/shift_rot/main_stage.py
index 0ab4c460da359276273b452f355d3ebcfcbf2a38..1a3b8eff0aadf54ade1b3d8819b5f0b0843103a7 100644 (file)
--- a/src/soc/fu/shift_rot/main_stage.py
+++ b/src/soc/fu/shift_rot/main_stage.py
@@ -1,11 +1,15 @@
+# License: LGPLv3
+# Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
+# Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
+
 # This stage is intended to do most of the work of executing shift
 # instructions, as well as carry and overflow generation. This module
 # however should not gate the carry or overflow, that's up to the
 # output stage
 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
 from nmutil.pipemodbase import PipeModBase
-from soc.fu.logical.pipe_data import LogicalOutputData
-from soc.fu.shift_rot.pipe_data import ShiftRotInputData
+from soc.fu.shift_rot.pipe_data import (ShiftRotOutputData,
+                                       ShiftRotInputData)
 from ieee754.part.partsig import PartitionedSignal
 from soc.decoder.power_enums import MicrOp
 from soc.fu.shift_rot.rotator import Rotator
@@ -24,7 +28,7 @@ class ShiftRotMainStage(PipeModBase):
         return ShiftRotInputData(self.pspec)
 
     def ospec(self):
-        return LogicalOutputData(self.pspec)
+        return ShiftRotOutputData(self.pspec)
 
     def elaborate(self, platform):
         m = Module()
@@ -84,6 +88,7 @@ class ShiftRotMainStage(PipeModBase):
 
         ###### sticky overflow and context, both pass-through #####
 
+        comb += self.o.xer_so.data.eq(self.i.xer_so)
         comb += self.o.ctx.eq(self.i.ctx)
 
         return m