comment out rlwinm. for now

[soc.git] / src / soc / fu / shift_rot / pipeline.py

diff --git a/src/soc/fu/shift_rot/pipeline.py b/src/soc/fu/shift_rot/pipeline.py
index 1080aa8debdaa56c571b8ab43c7638d080cfd92b..0449d37d964191fea1fb866f42292c201718100b 100644 (file)
--- a/src/soc/fu/shift_rot/pipeline.py
+++ b/src/soc/fu/shift_rot/pipeline.py
@@ -1,14 +1,14 @@
 from nmutil.singlepipe import ControlBase
 from nmutil.pipemodbase import PipeModBaseChain
-from soc.shift_rot.input_stage import ShiftRotInputStage
-from soc.shift_rot.main_stage import ShiftRotMainStage
-from soc.alu.output_stage import ALUOutputStage
+from soc.fu.shift_rot.input_stage import ShiftRotInputStage
+from soc.fu.shift_rot.main_stage import ShiftRotMainStage
+from soc.fu.logical.output_stage import LogicalOutputStage
 
 class ShiftRotStages(PipeModBaseChain):
     def get_chain(self):
         inp = ShiftRotInputStage(self.pspec)
         main = ShiftRotMainStage(self.pspec)
-        out = ALUOutputStage(self.pspec)
+        out = LogicalOutputStage(self.pspec)
         return [inp, main, out]