check problem state in OP_MTMSRD from original reg RA rather than

[soc.git] / src / soc / fu / shift_rot / rotator.py

diff --git a/src/soc/fu/shift_rot/rotator.py b/src/soc/fu/shift_rot/rotator.py
index 7ea9b0da54da304cdc505c718d8c0a97489b5662..7c3d811c8fa0402a70d5a3e1551e8ecb83873280 100644 (file)
--- a/src/soc/fu/shift_rot/rotator.py
+++ b/src/soc/fu/shift_rot/rotator.py
@@ -5,20 +5,24 @@ from nmigen.compat.sim import run_simulation
 from nmigen import (Elaboratable, Signal, Module, Const, Cat, Repl,
                     unsigned, signed)
 from soc.fu.shift_rot.rotl import ROTL
-from nmutil.extend import exts
 from nmigen.back.pysim import Settle
+from nmutil.extend import exts
+from nmutil.mask import Mask
 
 
 # note BE bit numbering
 def right_mask(m, mask_begin):
     ret = Signal(64, name="right_mask", reset_less=True)
     with m.If(mask_begin <= 64):
-        m.d.comb += ret.eq((1<<(64-mask_begin)) - 1)
+        m.d.comb += ret.eq((1 << (64-mask_begin)) - 1)
+    with m.Else():
+        m.d.comb += ret.eq(0)
     return ret
 
+
 def left_mask(m, mask_end):
     ret = Signal(64, name="left_mask", reset_less=True)
-    m.d.comb += ret.eq(~((1<<(63-mask_end)) - 1))
+    m.d.comb += ret.eq(~((1 << (63-mask_end)) - 1))
     return ret
 
 
@@ -40,11 +44,13 @@ class Rotator(Elaboratable):
         * clear_left = 1 when insn_type is OP_RLC or OP_RLCL
         * clear_right = 1 when insn_type is OP_RLC or OP_RLCR
     """
+
     def __init__(self):
         # input
         self.me = Signal(5, reset_less=True)        # ME field
         self.mb = Signal(5, reset_less=True)        # MB field
-        self.mb_extra = Signal(1, reset_less=True)  # extra bit of mb in MD-form
+        # extra bit of mb in MD-form
+        self.mb_extra = Signal(1, reset_less=True)
         self.ra = Signal(64, reset_less=True)       # RA
         self.rs = Signal(64, reset_less=True)       # RS
         self.shift = Signal(7, reset_less=True)     # RB[0:7]
@@ -133,8 +139,19 @@ class Rotator(Elaboratable):
             comb += me.eq(Cat(~sh[0:6], sh[6]))
 
         # Calculate left and right masks
-        comb += mr.eq(right_mask(m, mb))
-        comb += ml.eq(left_mask(m, me))
+        m.submodules.right_mask = right_mask = Mask(64)
+        with m.If(mb <= 64):
+            comb += right_mask.shift.eq(64-mb)
+            comb += mr.eq(right_mask.mask)
+        with m.Else():
+            comb += mr.eq(0)
+        #comb += mr.eq(right_mask(m, mb))
+
+        m.submodules.left_mask = left_mask = Mask(64)
+        comb += left_mask.shift.eq(63-me)
+        comb += ml.eq(~left_mask.mask)
+        #comb += ml.eq(left_mask(m, me))
+
 
         # Work out output mode
         # 00 for sl[wd]
@@ -162,6 +179,7 @@ class Rotator(Elaboratable):
 
         return m
 
+
 if __name__ == '__main__':
 
     m = Module()
@@ -175,8 +193,7 @@ if __name__ == '__main__':
             yield mb.eq(63-i)
             yield Settle()
             res = yield mr
-            print (i, hex(res))
+            print(i, hex(res))
 
     run_simulation(m, [loop()],
                    vcd_name="test_mask.vcd")
-