from soc.fu.shift_rot.pipeline import ShiftRotBasePipe
from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.alu.pipe_data import ALUPipeSpec
+from soc.fu.shift_rot.pipe_data import ShiftRotPipeSpec
import random
class TestCase:
self.sprs = sprs
self.name = name
-def get_rec_width(rec):
- recwidth = 0
- # Setup random inputs for dut.op
- for p in rec.ports():
- width = p.width
- recwidth += width
- return recwidth
def set_alu_inputs(alu, dec2, sim):
inputs = []
def set_extra_alu_inputs(alu, dec2, sim):
carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
- yield alu.p.data_i.carry_in.eq(carry)
+ carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+ yield alu.p.data_i.xer_ca[0].eq(carry)
+ yield alu.p.data_i.xer_ca[1].eq(carry32)
so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
- yield alu.p.data_i.so.eq(so)
+ yield alu.p.data_i.xer_so.eq(so)
# This test bench is a bit different than is usual. Initially when I
# should have. However, this was really slow, since it needed to
# create and tear down the dut and simulator for every test case.
-# Now, instead of doing that, every test case in ALUTestCase puts some
+# Now, instead of doing that, every test case in ShiftRotTestCase puts some
# data into the test_data list below, describing the instructions to
# be tested and the initial state. Once all the tests have been run,
# test_data gets passed to TestRunner which then sets up the DUT and
test_data = []
-class ALUTestCase(FHDLTestCase):
+class ShiftRotTestCase(FHDLTestCase):
def __init__(self, name):
super().__init__(name)
self.test_name = name
self.run_tst_program(Program(lst), initial_regs)
def test_ilang(self):
- rec = CompALUOpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ShiftRotPipeSpec(id_wid=2)
alu = ShiftRotBasePipe(pspec)
vl = rtlil.convert(alu, ports=alu.ports())
with open("pipeline.il", "w") as f:
m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- rec = CompALUOpSubset()
-
- pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
+ pspec = ShiftRotPipeSpec(id_wid=2)
m.submodules.alu = alu = ShiftRotBasePipe(pspec)
comb += alu.p.data_i.ctx.op.eq_from_execute1(pdecode2.e)
with sim.write_vcd("simulator.vcd", "simulator.gtkw",
traces=[]):
sim.run()
+
def check_extra_alu_outputs(self, alu, dec2, sim):
rc = yield dec2.e.rc.data
if rc: