include SPR.TB in SPR FU

[soc.git] / src / soc / fu / spr / main_stage.py

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index a73c6be9b897f174c88cf539d6086e4eee822a26..64676e441fcadc6cb128133311ce091342623b83 100644 (file)
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -57,7 +57,7 @@ class SPRMainStage(PipeModBase):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
-                                SPR.SRR1, SPR.XER, SPR.DEC):
+                                SPR.SRR1, SPR.XER, SPR.DEC, SPR.TB):
                         comb += fast1_o.data.eq(a_i)
                         comb += fast1_o.ok.eq(1)
                         # XER is constructed