format code

[soc.git] / src / soc / fu / spr / main_stage.py

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index b1262795a68aa767ea15862d938f8c09a8628d93..a73c6be9b897f174c88cf539d6086e4eee822a26 100644 (file)
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -7,16 +7,20 @@
 from nmigen import (Module, Signal, Cat)
 from nmutil.pipemodbase import PipeModBase
 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
-from soc.decoder.power_enums import MicrOp, SPR, XER_bits
+from openpower.decoder.power_enums import MicrOp, SPRfull, SPRreduced, XER_bits
 
-from soc.decoder.power_fields import DecodeFields
-from soc.decoder.power_fieldsn import SignalBitRange
-from soc.decoder.power_decoder2 import decode_spr_num
+from openpower.decoder.power_fields import DecodeFields
+from openpower.decoder.power_fieldsn import SignalBitRange
+from openpower.decoder.power_decoder2 import decode_spr_num
 
 
 class SPRMainStage(PipeModBase):
     def __init__(self, pspec):
         super().__init__(pspec, "spr_main")
+        # test if regfiles are reduced
+        self.regreduce_en = (hasattr(pspec, "regreduce") and
+                             (pspec.regreduce == True))
+
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
 
@@ -27,6 +31,10 @@ class SPRMainStage(PipeModBase):
         return SPROutputData(self.pspec)
 
     def elaborate(self, platform):
+        if self.regreduce_en:
+            SPR = SPRreduced
+        else:
+            SPR = SPRfull
         m = Module()
         comb = m.d.comb
         op = self.i.ctx.op
@@ -36,7 +44,6 @@ class SPRMainStage(PipeModBase):
         so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
         so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
         o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
-        state_i, state_o = self.i.state, self.o.state
 
         # take copy of D-Form TO field
         x_fields = self.fields.FormXFX
@@ -50,7 +57,7 @@ class SPRMainStage(PipeModBase):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
-                                SPR.SRR1, SPR.XER):
+                                SPR.SRR1, SPR.XER, SPR.DEC):
                         comb += fast1_o.data.eq(a_i)
                         comb += fast1_o.ok.eq(1)
                         # XER is constructed
@@ -66,12 +73,11 @@ class SPRMainStage(PipeModBase):
                             comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
                             comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
                             comb += ca_o.ok.eq(1)
-                    # STATE SPRs (dec, tb)
-                    with m.Case(SPR.DEC):
-                        comb += state_o.data.eq(a_i)
-                        comb += state_o.ok.eq(1)
 
                     # slow SPRs TODO
+                    with m.Default():
+                        comb += spr1_o.data.eq(a_i)
+                        comb += spr1_o.ok.eq(1)
 
             # move from SPRs
             with m.Case(MicrOp.OP_MFSPR):
@@ -79,13 +85,13 @@ class SPRMainStage(PipeModBase):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
-                                SPR.XER):
+                                SPR.XER, SPR.DEC, SPR.TB):
                         comb += o.data.eq(fast1_i)
                         with m.If(spr == SPR.XER):
                             # bits 0:31 and 35:43 are treated as reserved
                             # and return 0s when read using mfxer
                             comb += o[32:64].eq(0)       # MBS0 bits 0-31
-                            comb += o[63-43:64-35].eq(0) # MSB0 bits 35-43
+                            comb += o[63-43:64-35].eq(0)  # MSB0 bits 35-43
                             # sticky
                             comb += o[63-XER_bits['SO']].eq(so_i)
                             # overflow
@@ -94,13 +100,12 @@ class SPRMainStage(PipeModBase):
                             # carry
                             comb += o[63-XER_bits['CA']].eq(ca_i[0])
                             comb += o[63-XER_bits['CA32']].eq(ca_i[1])
-                    # STATE SPRs (dec, tb)
-                    with m.Case(SPR.DEC, SPR.TB):
-                        comb += o.data.eq(state_i)
                     with m.Case(SPR.TBU):
-                        comb += o.data[0:32].eq(state_i[32:64])
+                        comb += o.data[0:32].eq(fast1_i[32:64])
 
                     # slow SPRs TODO
+                    with m.Default():
+                        comb += o.data.eq(spr1_i)
 
         comb += self.o.ctx.eq(self.i.ctx)