Merge branch 'master' of git.libre-soc.org:soc

[soc.git] / src / soc / fu / spr / main_stage.py

diff --git a/src/soc/fu/spr/main_stage.py b/src/soc/fu/spr/main_stage.py
index 5786eff8637796c01896dc286ee107a33b7c746c..f4261b62a2b2d104c9edfa88262f27a97d9498a3 100644 (file)
--- a/src/soc/fu/spr/main_stage.py
+++ b/src/soc/fu/spr/main_stage.py
@@ -4,23 +4,19 @@
 * https://libre-soc.org/openpower/isa/sprset/
 """
 
-from nmigen import (Module, Signal, Cat, Mux, Const, signed)
+from nmigen import (Module, Signal, Cat)
 from nmutil.pipemodbase import PipeModBase
-from nmutil.extend import exts
 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
-from soc.fu.branch.main_stage import br_ext
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp, SPR, XER_bits
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
-
-def decode_spr_num(spr):
-    return Cat(spr[5:10], spr[0:5])
+from soc.decoder.power_decoder2 import decode_spr_num
 
 
 class SPRMainStage(PipeModBase):
     def __init__(self, pspec):
-        super().__init__(pspec, "main")
+        super().__init__(pspec, "spr_main")
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
 
@@ -43,13 +39,13 @@ class SPRMainStage(PipeModBase):
 
         # take copy of D-Form TO field
         x_fields = self.fields.FormXFX
-        spr = Signal(x_fields.SPR[0:-1].shape())
-        comb += spr.eq(decode_spr_num(i_fields.SPR[0:-1]))
+        spr = Signal(len(x_fields.SPR))
+        comb += spr.eq(decode_spr_num(x_fields.SPR))
 
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
             #### MTSPR ####
-            with m.Case(InternalOp.OP_MTSPR):
+            with m.Case(MicrOp.OP_MTSPR):
                 with m.Switch(spr):
                     # fast SPRs first
                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1):
@@ -71,7 +67,7 @@ class SPRMainStage(PipeModBase):
                     # slow SPRs TODO
 
             # move from SPRs
-            with m.Case(InternalOp.OP_MFSPR):
+            with m.Case(MicrOp.OP_MFSPR):
                 comb += o.ok.eq(1)
                 with m.Switch(spr):
                     # fast SPRs first