convert branch pipeline to use msr/cia as immediates

[soc.git] / src / soc / fu / spr / test / test_pipe_caller.py

diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py
index 3ba1ac3dff97afa9ce637a599e5337f27363a174..e20c55e0ff5a4d00b1b967be588b6d0070f6a8f5 100644 (file)
--- a/src/soc/fu/spr/test/test_pipe_caller.py
+++ b/src/soc/fu/spr/test/test_pipe_caller.py
@@ -210,6 +210,7 @@ class TestRunner(FHDLTestCase):
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
                     yield pdecode2.msr.eq(msr) # set MSR in pdecode2
+                    yield pdecode2.cia.eq(pc) # set PC in pdecode2
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()