continue debugging trap pipeline

[soc.git] / src / soc / fu / test / common.py

diff --git a/src/soc/fu/test/common.py b/src/soc/fu/test/common.py
index 9569dfd928291d92e2b18aac9c9498b30f89ce29..7c46bf372dc11058a6ca5640a18ba16029a610dc 100644 (file)
--- a/src/soc/fu/test/common.py
+++ b/src/soc/fu/test/common.py
@@ -3,8 +3,9 @@ Bugreports:
 * https://bugs.libre-soc.org/show_bug.cgi?id=361
 """
 
-from soc.decoder.power_enums import XER_bits
+from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
 from soc.regfile.util import fast_reg_to_spr # HACK!
+from soc.regfile.regfiles import FastRegs
 
 
 class TestCase:
@@ -28,6 +29,17 @@ class TestCase:
 
 class ALUHelpers:
 
+    def get_sim_fast_reg(res, sim, dec2, reg, name):
+        spr_sel = fast_reg_to_spr(reg)
+        spr_data = sim.spr[spr_sel].value
+        res[name] = spr_data
+
+    def get_sim_cia(res, sim, dec2):
+        res['cia'] = sim.pc.CIA.value
+
+    def get_sim_msr(res, sim, dec2):
+        res['msr'] = sim.msr.value
+
     def get_sim_fast_spr1(res, sim, dec2):
         fast1_en = yield dec2.e.read_fast1.ok
         if fast1_en:
@@ -69,6 +81,13 @@ class ALUHelpers:
             data = yield dec2.e.read_reg3.data
             res['rc'] = sim.gpr(data).value
 
+    def get_rd_sim_xer_ca(res, sim, dec2):
+        cry_in = yield dec2.e.input_carry
+        if cry_in == CryIn.CA.value:
+            expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+            expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+            res['xer_ca'] = expected_carry | (expected_carry32 << 1)
+
     def set_int_ra(alu, dec2, inp):
         # TODO: immediate RA zero.
         if 'ra' in inp:
@@ -103,6 +122,10 @@ class ALUHelpers:
             print ("extra inputs: so", so)
             yield alu.p.data_i.xer_so.eq(so)
 
+    def set_fast_msr(alu, dec2, inp):
+        if 'msr' in inp:
+            yield alu.p.data_i.msr.eq(inp['msr'])
+
     def set_fast_cia(alu, dec2, inp):
         if 'cia' in inp:
             yield alu.p.data_i.cia.eq(inp['cia'])
@@ -133,10 +156,35 @@ class ALUHelpers:
         else:
             yield alu.p.data_i.full_cr.eq(0)
 
+    def get_fast_spr1(res, alu, dec2):
+        spr1_valid = yield alu.n.data_o.spr1.ok
+        if spr1_valid:
+            res['spr1'] = yield alu.n.data_o.spr1.data
+
+    def get_fast_spr2(res, alu, dec2):
+        spr2_valid = yield alu.n.data_o.spr2.ok
+        if spr2_valid:
+            res['spr2'] = yield alu.n.data_o.spr2.data
+
+    def get_fast_nia(res, alu, dec2):
+        nia_valid = yield alu.n.data_o.nia.ok
+        if nia_valid:
+            res['nia'] = yield alu.n.data_o.nia.data
+
+    def get_fast_msr(res, alu, dec2):
+        msr_valid = yield alu.n.data_o.msr.ok
+        if msr_valid:
+            res['msr'] = yield alu.n.data_o.msr.data
+
+    def get_int_o1(res, alu, dec2):
+        out_reg_valid = yield dec2.e.write_ea.ok
+        if out_reg_valid:
+            res['o1'] = yield alu.n.data_o.o1.data
+
     def get_int_o(res, alu, dec2):
         out_reg_valid = yield dec2.e.write_reg.ok
         if out_reg_valid:
-            res['o'] = yield alu.n.data_o.o.data 
+            res['o'] = yield alu.n.data_o.o.data
 
     def get_cr_a(res, alu, dec2):
         cridx_ok = yield dec2.e.write_cr.ok
@@ -166,13 +214,33 @@ class ALUHelpers:
             write_reg_idx = yield dec2.e.write_reg.data
             res['o'] = sim.gpr(write_reg_idx).value
 
+    def get_sim_int_o1(res, sim, dec2):
+        out_reg_valid = yield dec2.e.write_ea.ok
+        if out_reg_valid:
+            write_reg_idx = yield dec2.e.write_ea.data
+            res['o1'] = sim.gpr(write_reg_idx).value
+
     def get_wr_sim_cr_a(res, sim, dec2):
         cridx_ok = yield dec2.e.write_cr.ok
         if cridx_ok:
             cridx = yield dec2.e.write_cr.data
             res['cr_a'] = sim.crl[cridx].get_range().value
 
-    def get_sim_xer_ca(res, sim, dec2):
+    def get_wr_fast_spr2(res, sim, dec2):
+        ok = yield dec2.e.write_fast2.ok
+        if ok:
+            spr_num = yield dec2.e.write_fast2.data
+            spr_name = spr_dict[spr_num]
+            res['spr2'] = sim.spr[spr_name]
+
+    def get_wr_fast_spr1(res, sim, dec2):
+        ok = yield dec2.e.write_fast1.ok
+        if ok:
+            spr_num = yield dec2.e.write_fast1.data
+            spr_name = spr_dict[spr_num]
+            res['spr1'] = sim.spr[spr_name]
+
+    def get_wr_sim_xer_ca(res, sim, dec2):
         cry_out = yield dec2.e.output_carry
         if cry_out:
             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
@@ -193,6 +261,13 @@ class ALUHelpers:
         if oe and oe_ok:
             res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
 
+    def check_int_o1(dut, res, sim_o, msg):
+        if 'o1' in res:
+            expected = sim_o['o1']
+            alu_out = res['o1']
+            print(f"expected {expected:x}, actual: {alu_out:x}")
+            dut.assertEqual(expected, alu_out, msg)
+
     def check_int_o(dut, res, sim_o, msg):
         if 'o' in res:
             expected = sim_o['o']