-from soc.decoder.power_enums import XER_bits
+"""
+Bugreports:
+* https://bugs.libre-soc.org/show_bug.cgi?id=361
+"""
+
+from soc.decoder.power_enums import XER_bits, CryIn, spr_dict
+from soc.regfile.util import fast_reg_to_spr # HACK!
+from soc.regfile.regfiles import FastRegs
class TestCase:
class ALUHelpers:
+ def get_sim_fast_reg(res, sim, dec2, reg, name):
+ spr_sel = fast_reg_to_spr(reg)
+ spr_data = sim.spr[spr_sel].value
+ res[name] = spr_data
+
+ def get_sim_cia(res, sim, dec2):
+ return self.get_sim_fast_reg(res, sim, dec2, FastRegs.PC, 'pc')
+
+ def get_sim_msr(res, sim, dec2):
+ return self.get_sim_fast_reg(res, sim, dec2, FastRegs.MSR, 'msr')
+
+ def get_sim_fast_spr1(res, sim, dec2):
+ fast1_en = yield dec2.e.read_fast1.ok
+ if fast1_en:
+ fast1_sel = yield dec2.e.read_fast1.data
+ spr1_sel = fast_reg_to_spr(fast1_sel)
+ spr1_data = sim.spr[spr1_sel].value
+ res['spr1'] = spr1_data
+
+ def get_sim_fast_spr2(res, sim, dec2):
+ fast2_en = yield dec2.e.read_fast2.ok
+ if fast2_en:
+ fast2_sel = yield dec2.e.read_fast2.data
+ spr2_sel = fast_reg_to_spr(fast2_sel)
+ spr2_data = sim.spr[spr2_sel].value
+ res['spr2'] = spr2_data
+
+ def get_sim_cr_a(res, sim, dec2):
+ cridx_ok = yield dec2.e.read_cr1.ok
+ if cridx_ok:
+ cridx = yield dec2.e.read_cr1.data
+ res['cr_a'] = sim.crl[cridx].get_range().value
+
+ def get_sim_int_ra(res, sim, dec2):
+ # TODO: immediate RA zero
+ reg1_ok = yield dec2.e.read_reg1.ok
+ if reg1_ok:
+ data1 = yield dec2.e.read_reg1.data
+ res['ra'] = sim.gpr(data1).value
+
+ def get_sim_int_rb(res, sim, dec2):
+ reg2_ok = yield dec2.e.read_reg2.ok
+ if reg2_ok:
+ data = yield dec2.e.read_reg2.data
+ res['rb'] = sim.gpr(data).value
+
+ def get_sim_int_rc(res, sim, dec2):
+ reg3_ok = yield dec2.e.read_reg3.ok
+ if reg3_ok:
+ data = yield dec2.e.read_reg3.data
+ res['rc'] = sim.gpr(data).value
+
+ def get_rd_sim_xer_ca(res, sim, dec2):
+ cry_in = yield dec2.e.input_carry
+ if cry_in == CryIn.CA.value:
+ expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
+ expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
+ res['xer_ca'] = expected_carry | (expected_carry32 << 1)
+
def set_int_ra(alu, dec2, inp):
+ # TODO: immediate RA zero.
if 'ra' in inp:
yield alu.p.data_i.ra.eq(inp['ra'])
else:
print ("extra inputs: so", so)
yield alu.p.data_i.xer_so.eq(so)
+ def set_fast_msr(alu, dec2, inp):
+ if 'msr' in inp:
+ yield alu.p.data_i.msr.eq(inp['msr'])
+
def set_fast_cia(alu, dec2, inp):
if 'cia' in inp:
yield alu.p.data_i.cia.eq(inp['cia'])
else:
yield alu.p.data_i.full_cr.eq(0)
+ def get_fast_spr1(res, alu, dec2):
+ spr1_valid = yield alu.n.data_o.spr1.ok
+ if spr1_valid:
+ res['spr1'] = yield alu.n.data_o.spr1.data
+
+ def get_fast_spr2(res, alu, dec2):
+ spr2_valid = yield alu.n.data_o.spr2.ok
+ if spr2_valid:
+ res['spr2'] = yield alu.n.data_o.spr2.data
+
+ def get_fast_nia(res, alu, dec2):
+ nia_valid = yield alu.n.data_o.nia.ok
+ if nia_valid:
+ res['nia'] = yield alu.n.data_o.nia.data
+
+ def get_fast_msr(res, alu, dec2):
+ msr_valid = yield alu.n.data_o.msr.ok
+ if msr_valid:
+ res['msr'] = yield alu.n.data_o.msr.data
+
+ def get_int_o1(res, alu, dec2):
+ out_reg_valid = yield dec2.e.write_ea.ok
+ if out_reg_valid:
+ res['o1'] = yield alu.n.data_o.o1.data
+
def get_int_o(res, alu, dec2):
out_reg_valid = yield dec2.e.write_reg.ok
if out_reg_valid:
- res['o'] = yield alu.n.data_o.o.data
+ res['o'] = yield alu.n.data_o.o.data
def get_cr_a(res, alu, dec2):
cridx_ok = yield dec2.e.write_cr.ok
write_reg_idx = yield dec2.e.write_reg.data
res['o'] = sim.gpr(write_reg_idx).value
- def get_sim_cr_a(res, sim, dec2):
+ def get_sim_int_o1(res, sim, dec2):
+ out_reg_valid = yield dec2.e.write_ea.ok
+ if out_reg_valid:
+ write_reg_idx = yield dec2.e.write_ea.data
+ res['o1'] = sim.gpr(write_reg_idx).value
+
+ def get_wr_sim_cr_a(res, sim, dec2):
cridx_ok = yield dec2.e.write_cr.ok
if cridx_ok:
cridx = yield dec2.e.write_cr.data
res['cr_a'] = sim.crl[cridx].get_range().value
- def get_sim_xer_ca(res, sim, dec2):
+ def get_wr_fast_spr2(res, sim, dec2):
+ ok = yield dec2.e.write_fast2.ok
+ if ok:
+ spr_num = yield dec2.e.write_fast2.data
+ spr_name = spr_dict[spr_num]
+ res['spr2'] = sim.spr[spr_name]
+
+ def get_wr_fast_spr1(res, sim, dec2):
+ ok = yield dec2.e.write_fast1.ok
+ if ok:
+ spr_num = yield dec2.e.write_fast1.data
+ spr_name = spr_dict[spr_num]
+ res['spr1'] = sim.spr[spr_name]
+
+ def get_wr_sim_xer_ca(res, sim, dec2):
cry_out = yield dec2.e.output_carry
if cry_out:
expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
if oe and oe_ok:
res['xer_so'] = 1 if sim.spr['XER'][XER_bits['SO']] else 0
+ def check_int_o1(dut, res, sim_o, msg):
+ if 'o1' in res:
+ expected = sim_o['o1']
+ alu_out = res['o1']
+ print(f"expected {expected:x}, actual: {alu_out:x}")
+ dut.assertEqual(expected, alu_out, msg)
+
def check_int_o(dut, res, sim_o, msg):
if 'o' in res:
expected = sim_o['o']
projects / soc.git / blobdiff