forgot to clean up workspace in source

[soc.git] / src / soc / fu / trap / main_stage.py

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 0ddb2823f13243ba8a54aa501b2c641514092980..325fb373546673df3ec19a15554e775bcc6fe9a9 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -14,14 +14,12 @@ from nmutil.pipemodbase import PipeModBase
 from nmutil.extend import exts
 from soc.fu.trap.pipe_data import TrapInputData, TrapOutputData
 from soc.fu.branch.main_stage import br_ext
-from soc.decoder.power_enums import InternalOp
+from soc.decoder.power_enums import MicrOp
 
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR,
-                                        TT_ILLEG)
-from soc.consts import MSR, PI
+from soc.consts import MSR, PI, TT
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):
@@ -146,7 +144,7 @@ class TrapMainStage(PipeModBase):
         # TODO: some #defines for the bits n stuff.
         with m.Switch(op.insn_type):
             #### trap ####
-            with m.Case(InternalOp.OP_TRAP):
+            with m.Case(MicrOp.OP_TRAP):
                 # trap instructions (tw, twi, td, tdi)
                 with m.If(should_trap):
                     # generate trap-type program interrupt
@@ -154,17 +152,17 @@ class TrapMainStage(PipeModBase):
                     with m.If(traptype == 0):
                         # say trap occurred (see 3.0B Book III 7.5.9)
                         comb += srr1_o.data[PI.TRAP].eq(1)
-                    with m.If(traptype & TT_PRIV):
+                    with m.If(traptype & TT.PRIV):
                         comb += srr1_o.data[PI.PRIV].eq(1)
-                    with m.If(traptype & TT_FP):
+                    with m.If(traptype & TT.FP):
                         comb += srr1_o.data[PI.FP].eq(1)
-                    with m.If(traptype & TT_ADDR):
+                    with m.If(traptype & TT.ADDR):
                         comb += srr1_o.data[PI.ADR].eq(1)
-                    with m.If(traptype & TT_ILLEG):
+                    with m.If(traptype & TT.ILLEG):
                         comb += srr1_o.data[PI.ILLEG].eq(1)
 
             # move to MSR
-            with m.Case(InternalOp.OP_MTMSRD, InternalOp.OP_MTMSR):
+            with m.Case(MicrOp.OP_MTMSRD, MicrOp.OP_MTMSR):
                 L = self.fields.FormX.L[0:-1] # X-Form field L
                 # start with copy of msr
                 comb += msr_o.eq(msr_i)
@@ -175,18 +173,23 @@ class TrapMainStage(PipeModBase):
                 with m.Else():
                     # Architecture says to leave out bits 3 (HV), 51 (ME)
                     # and 63 (LE) (IBM bit numbering)
-                    for stt, end in [(1,12), (13, 60), (61, 64)]:
-                        comb += msr_o.data[stt:end].eq(a_i[stt:end])
+                    with m.If(op.insn_type == MicrOp.OP_MTMSRD):
+                        for stt, end in [(1,12), (13, 60), (61, 64)]:
+                            comb += msr_o.data[stt:end].eq(a_i[stt:end])
+                    with m.Else():
+                        # mtmsr - 32-bit, only room for bottom 32 LSB flags
+                        for stt, end in [(1,12), (13, 32)]:
+                            comb += msr_o.data[stt:end].eq(a_i[stt:end])
                     msr_check_pr(m, msr_o.data)
                 comb += msr_o.ok.eq(1)
 
             # move from MSR
-            with m.Case(InternalOp.OP_MFMSR):
+            with m.Case(MicrOp.OP_MFMSR):
                 # TODO: some of the bits need zeroing?  apparently not
                 comb += o.data.eq(msr_i)
                 comb += o.ok.eq(1)
 
-            with m.Case(InternalOp.OP_RFID):
+            with m.Case(MicrOp.OP_RFID):
                 # XXX f_out.virt_mode <= b_in(MSR.IR) or b_in(MSR.PR);
                 # XXX f_out.priv_mode <= not b_in(MSR.PR);
 
@@ -210,15 +213,15 @@ class TrapMainStage(PipeModBase):
                 comb += msr_o.ok.eq(1)
 
             # OP_SC
-            with m.Case(InternalOp.OP_SC):
-                # TODO: scv must generate illegal instruction.  this is
-                # the decoder's job, not ours, here.
+            with m.Case(MicrOp.OP_SC):
+                # tscb is not covered here. currently an illegal instruction.
+                # raising that the decoder's job, not ours, here.
 
                 # jump to the trap address, return at cia+4
                 self.trap(m, 0xc00, cia_i+4)
 
             # TODO (later)
-            #with m.Case(InternalOp.OP_ADDPCIS):
+            #with m.Case(MicrOp.OP_ADDPCIS):
             #    pass
 
         comb += self.o.ctx.eq(self.i.ctx)