from soc.decoder.power_fields import DecodeFields
from soc.decoder.power_fieldsn import SignalBitRange
-from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR,
- TT_ILLEG)
-from soc.consts import MSR, PI
+from soc.consts import MSR, PI, TT
def msr_copy(msr_o, msr_i, zero_me=True):
with m.If(traptype == 0):
# say trap occurred (see 3.0B Book III 7.5.9)
comb += srr1_o.data[PI.TRAP].eq(1)
- with m.If(traptype & TT_PRIV):
+ with m.If(traptype & TT.PRIV):
comb += srr1_o.data[PI.PRIV].eq(1)
- with m.If(traptype & TT_FP):
+ with m.If(traptype & TT.FP):
comb += srr1_o.data[PI.FP].eq(1)
- with m.If(traptype & TT_ADDR):
+ with m.If(traptype & TT.ADDR):
comb += srr1_o.data[PI.ADR].eq(1)
- with m.If(traptype & TT_ILLEG):
+ with m.If(traptype & TT.ILLEG):
comb += srr1_o.data[PI.ILLEG].eq(1)
# move to MSR
# OP_SC
with m.Case(MicrOp.OP_SC):
- # TODO: scv must generate illegal instruction. this is
- # the decoder's job, not ours, here.
+ # tscb is not covered here. currently an illegal instruction.
+ # raising that the decoder's job, not ours, here.
# jump to the trap address, return at cia+4
self.trap(m, 0xc00, cia_i+4)