Rework SC properties to conform to style

[soc.git] / src / soc / fu / trap / main_stage.py

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 769ae86386da336f04abdfe7a0477cf3339c9c61..39f4326d1697d70a86aadbd892bbeef2057c4970 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -19,9 +19,7 @@ from soc.decoder.power_enums import MicrOp
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-from soc.decoder.power_decoder2 import (TT_FP, TT_PRIV, TT_TRAP, TT_ADDR,
-                                        TT_ILLEG)
-from soc.consts import MSR, PI
+from soc.consts import MSR, PI, TT
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):
@@ -154,13 +152,13 @@ class TrapMainStage(PipeModBase):
                     with m.If(traptype == 0):
                         # say trap occurred (see 3.0B Book III 7.5.9)
                         comb += srr1_o.data[PI.TRAP].eq(1)
-                    with m.If(traptype & TT_PRIV):
+                    with m.If(traptype & TT.PRIV):
                         comb += srr1_o.data[PI.PRIV].eq(1)
-                    with m.If(traptype & TT_FP):
+                    with m.If(traptype & TT.FP):
                         comb += srr1_o.data[PI.FP].eq(1)
-                    with m.If(traptype & TT_ADDR):
+                    with m.If(traptype & TT.ADDR):
                         comb += srr1_o.data[PI.ADR].eq(1)
-                    with m.If(traptype & TT_ILLEG):
+                    with m.If(traptype & TT.ILLEG):
                         comb += srr1_o.data[PI.ILLEG].eq(1)
 
             # move to MSR
@@ -175,8 +173,13 @@ class TrapMainStage(PipeModBase):
                 with m.Else():
                     # Architecture says to leave out bits 3 (HV), 51 (ME)
                     # and 63 (LE) (IBM bit numbering)
-                    for stt, end in [(1,12), (13, 60), (61, 64)]:
-                        comb += msr_o.data[stt:end].eq(a_i[stt:end])
+                    with m.If(op.insn_type == MicrOp.OP_MTMSRD):
+                        for stt, end in [(1,12), (13, 60), (61, 64)]:
+                            comb += msr_o.data[stt:end].eq(a_i[stt:end])
+                    with m.Else():
+                        # mtmsr - 32-bit, only room for bottom 32 LSB flags
+                        for stt, end in [(1,12), (13, 32)]:
+                            comb += msr_o.data[stt:end].eq(a_i[stt:end])
                     msr_check_pr(m, msr_o.data)
                 comb += msr_o.ok.eq(1)
 
@@ -193,26 +196,33 @@ class TrapMainStage(PipeModBase):
                 # return addr was in srr0
                 comb += nia_o.data.eq(br_ext(srr0_i[2:]))
                 comb += nia_o.ok.eq(1)
-                # MSR was in srr1
+
+                # MSR was in srr1: copy it over, however *caveats below*
                 comb += msr_copy(msr_o.data, srr1_i, zero_me=False) # don't zero
+
+                # check problem state
                 msr_check_pr(m, msr_o.data)
 
-                # hypervisor stuff
-                comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV] & srr1_i[MSR.HV])
-                comb += msr_o.data[MSR.ME].eq((msr_i[MSR.HV] & srr1_i[MSR.HV]) |
-                                             (~msr_i[MSR.HV] & srr1_i[MSR.HV]))
-                # don't understand but it's in the spec
-                with m.If((msr_i[63-31:63-29] != Const(0b010, 3)) |
-                          (srr1_i[63-31:63-29] != Const(0b000, 3))):
-                    comb += msr_o.data[63-31:63-29].eq(srr1_i[63-31:63-29])
-                with m.Else():
-                    comb += msr_o.data[63-31:63-29].eq(msr_i[63-31:63-29])
+                # hypervisor stuff.  here: bits 3 (HV) and 51 (ME) were
+                # copied over by msr_copy but if HV was not set we need
+                # the *original* (msr_i) bits
+                with m.If(~msr_i[MSR.HV]):
+                    comb += msr_o.data[MSR.HV].eq(msr_i[MSR.HV])
+                    comb += msr_o.data[MSR.ME].eq(msr_i[MSR.ME])
+
+                # don't understand but it's in the spec.  again: bits 32-34
+                # are copied from srr1_i and need *restoring* to msr_i
+                bits = slice(63-31,63-29+1) # bits 29, 30, 31 (Power notation)
+                with m.If((msr_i[bits] == Const(0b010, 3)) &
+                          (srr1_i[bits] == Const(0b000, 3))):
+                    comb += msr_o.data[bits].eq(msr_i[bits])
+
                 comb += msr_o.ok.eq(1)
 
             # OP_SC
             with m.Case(MicrOp.OP_SC):
-                # TODO: scv must generate illegal instruction.  this is
-                # the decoder's job, not ours, here.
+                # scv is not covered here. currently an illegal instruction.
+                # raising "illegal" is the decoder's job, not ours, here.
 
                 # jump to the trap address, return at cia+4
                 self.trap(m, 0xc00, cia_i+4)