reduce regfile ports by creating separate STATE regfile

[soc.git] / src / soc / fu / trap / pipe_data.py

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index de55cf2e57072bf35623581603a60373d459e4d9..863710c5879c91f958b6bfcbef5bb3aa26658684 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -7,6 +7,8 @@ class TrapInputData(IntegerData):
                ('INT', 'rb', '0:63'),  # RB/immediate
                ('FAST', 'fast1', '0:63'), # SRR0
                ('FAST', 'fast2', '0:63'), # SRR1
+                # note here that neither MSR nor CIA are read as regs: they are
+                # passed in as incoming "State", via the CompTrapOpSubset
                ] 
     def __init__(self, pspec):
         super().__init__(pspec, False)
@@ -19,8 +21,8 @@ class TrapOutputData(IntegerData):
     regspec = [('INT', 'o', '0:63'),     # RA
                ('FAST', 'fast1', '0:63'), # SRR0 SPR
                ('FAST', 'fast2', '0:63'), # SRR1 SPR
-               ('FAST', 'nia', '0:63'),  # NIA (Next PC)
-               ('FAST', 'msr', '0:63')]  # MSR
+               ('STATE', 'nia', '0:63'),  # NIA (Next PC)
+               ('STATE', 'msr', '0:63')]  # MSR
     def __init__(self, pspec):
         super().__init__(pspec, True)
         # convenience