convert ALU to new accumulator style

[soc.git] / src / soc / fu / trap / pipe_data.py

diff --git a/src/soc/fu/trap/pipe_data.py b/src/soc/fu/trap/pipe_data.py
index d2de8552a62a55bada4a5e83726c273ef943ac83..de55cf2e57072bf35623581603a60373d459e4d9 100644 (file)
--- a/src/soc/fu/trap/pipe_data.py
+++ b/src/soc/fu/trap/pipe_data.py
@@ -7,8 +7,7 @@ class TrapInputData(IntegerData):
                ('INT', 'rb', '0:63'),  # RB/immediate
                ('FAST', 'fast1', '0:63'), # SRR0
                ('FAST', 'fast2', '0:63'), # SRR1
-               ('FAST', 'cia', '0:63'),  # Program counter (current)
-               ('FAST', 'msr', '0:63')]  # MSR
+               ] 
     def __init__(self, pspec):
         super().__init__(pspec, False)
         # convenience