adding mtspr tests

[soc.git] / src / soc / fu / trap / test / test_pipe_caller.py

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index 5ab41ee9ead831f4e19036f9a0c451bd36841235..25514730c75c5cba8fafa48aa76a38ddbccd9d0f 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -26,6 +26,7 @@ def get_cu_inputs(dec2, sim):
     yield from ALUHelpers.get_sim_int_ra(res, sim, dec2) # RA
     yield from ALUHelpers.get_sim_int_rb(res, sim, dec2) # RB
     yield from ALUHelpers.get_sim_fast_spr1(res, sim, dec2) # SPR1
+    yield from ALUHelpers.get_sim_fast_spr2(res, sim, dec2) # SPR2
     ALUHelpers.get_sim_cia(res, sim, dec2) # PC
     ALUHelpers.get_sim_msr(res, sim, dec2) # MSR
 
@@ -43,6 +44,8 @@ def set_alu_inputs(alu, dec2, sim):
     inp = yield from get_cu_inputs(dec2, sim)
     yield from ALUHelpers.set_int_ra(alu, dec2, inp)
     yield from ALUHelpers.set_int_rb(alu, dec2, inp)
+    yield from ALUHelpers.set_fast_spr1(alu, dec2, inp) # SPR1
+    yield from ALUHelpers.set_fast_spr2(alu, dec2, inp) # SPR1
 
     yield from ALUHelpers.set_cia(alu, dec2, inp)
     yield from ALUHelpers.set_msr(alu, dec2, inp)
@@ -104,6 +107,25 @@ class TrapTestCase(FHDLTestCase):
             initial_regs[2] = 1
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_3_mtmsr_0(self):
+        lst = ["mtmsr 1,0"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_3_mtmsr_1(self):
+        lst = ["mtmsr 1,1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_999_illegal(self):
+        # ok, um this is a bit of a cheat: use an instruction we know
+        # is not implemented by either ISACaller or the core
+        lst = ["tbegin."]
+        initial_regs = [0] * 32
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_ilang(self):
         pspec = TrapPipeSpec(id_wid=2)
         alu = TrapBasePipe(pspec)
@@ -163,7 +185,7 @@ class TestRunner(FHDLTestCase):
                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
-                    fn_unit = yield pdecode2.e.fn_unit
+                    fn_unit = yield pdecode2.e.do.fn_unit
                     self.assertEqual(fn_unit, Function.TRAP.value)
                     yield from set_alu_inputs(alu, pdecode2, sim)
                     yield
@@ -188,7 +210,7 @@ class TestRunner(FHDLTestCase):
 
     def check_alu_outputs(self, alu, dec2, sim, code):
 
-        rc = yield dec2.e.rc.data
+        rc = yield dec2.e.do.rc.data
         cridx_ok = yield dec2.e.write_cr.ok
         cridx = yield dec2.e.write_cr.data
 
@@ -208,17 +230,18 @@ class TestRunner(FHDLTestCase):
         print ("output", res)
 
         yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
-        yield from ALUHelpers.get_sim_xer_ov(sim_o, sim, dec2)
-        yield from ALUHelpers.get_wr_sim_xer_ca(sim_o, sim, dec2)
-        ALUHelpers.get_sim_cia(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_fast_spr1(sim_o, sim, dec2)
+        yield from ALUHelpers.get_wr_fast_spr2(sim_o, sim, dec2)
+        ALUHelpers.get_sim_nia(sim_o, sim, dec2)
         ALUHelpers.get_sim_msr(sim_o, sim, dec2)
 
-        ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
-        ALUHelpers.check_xer_ov(self, res, sim_o, code)
-        ALUHelpers.check_xer_ca(self, res, sim_o, code)
+        print ("sim output", sim_o)
+
         ALUHelpers.check_int_o(self, res, sim_o, code)
-        ALUHelpers.check_xer_so(self, res, sim_o, code)
+        ALUHelpers.check_fast_spr1(self, res, sim_o, code)
+        ALUHelpers.check_fast_spr2(self, res, sim_o, code)
+        ALUHelpers.check_nia(self, res, sim_o, code)
+        ALUHelpers.check_msr(self, res, sim_o, code)
 
 
 if __name__ == "__main__":