adding mtspr tests

[soc.git] / src / soc / fu / trap / test / test_pipe_caller.py

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index b27cd0b2583e62fe310939c4eec1c33a116c999b..25514730c75c5cba8fafa48aa76a38ddbccd9d0f 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -107,6 +107,25 @@ class TrapTestCase(FHDLTestCase):
             initial_regs[2] = 1
             self.run_tst_program(Program(lst), initial_regs)
 
+    def test_3_mtmsr_0(self):
+        lst = ["mtmsr 1,0"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_3_mtmsr_1(self):
+        lst = ["mtmsr 1,1"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 0xffffffffffffffff
+        self.run_tst_program(Program(lst), initial_regs)
+
+    def test_999_illegal(self):
+        # ok, um this is a bit of a cheat: use an instruction we know
+        # is not implemented by either ISACaller or the core
+        lst = ["tbegin."]
+        initial_regs = [0] * 32
+        self.run_tst_program(Program(lst), initial_regs)
+
     def test_ilang(self):
         pspec = TrapPipeSpec(id_wid=2)
         alu = TrapBasePipe(pspec)
@@ -222,6 +241,7 @@ class TestRunner(FHDLTestCase):
         ALUHelpers.check_fast_spr1(self, res, sim_o, code)
         ALUHelpers.check_fast_spr2(self, res, sim_o, code)
         ALUHelpers.check_nia(self, res, sim_o, code)
+        ALUHelpers.check_msr(self, res, sim_o, code)
 
 
 if __name__ == "__main__":