radix: reading first page table entry

[soc.git] / src / soc / interrupts / xics.py

diff --git a/src/soc/interrupts/xics.py b/src/soc/interrupts/xics.py
index 23e966470c50e5d45b64559d3b40e76abb658632..ede33a1b03913307f33ce8080652d315c0403ce9 100644 (file)
--- a/src/soc/interrupts/xics.py
+++ b/src/soc/interrupts/xics.py
@@ -78,7 +78,7 @@ class XICS_ICP(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec), name="icp_wb")
+        self.bus = Record(make_wb_layout(spec, cti=False), name="icp_wb")
         self.ics_i = ICS2ICP("ics_i")
         self.core_irq_o = Signal()
 
@@ -93,8 +93,9 @@ class XICS_ICP(Elaboratable):
         # We delay core_irq_out by a cycle to help with timing
         sync += self.core_irq_o.eq(r.irq)
 
-        comb += self.bus.dat_r.eq(r.wb_rd_data)
-        comb += self.bus.ack.eq(r.wb_ack)
+        comb += self.bus.ack.eq(r.wb_ack & self.bus.cyc)
+        with m.If(self.bus.ack):
+            comb += self.bus.dat_r.eq(r.wb_rd_data)
 
         v = RegInternal()
         xirr_accept_rd = Signal()
@@ -231,7 +232,7 @@ class XICS_ICS(Elaboratable):
         spec.addr_wid = 30
         spec.mask_wid = 4
         spec.reg_wid = 32
-        self.bus = Record(make_wb_layout(spec), name="ics_wb")
+        self.bus = Record(make_wb_layout(spec, cti=False), name="ics_wb")
 
         self.int_level_i = Signal(SRC_NUM)
         self.icp_o = ICS2ICP("icp_o")