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almost all tests work
[soc.git]
/
src
/
soc
/
iommu
/
axi_rab
/
ram_tp_write_first.py
diff --git
a/src/soc/iommu/axi_rab/ram_tp_write_first.py
b/src/soc/iommu/axi_rab/ram_tp_write_first.py
index 7a21969c2e303bc963acaa03a012e06114483ceb..8fd2abb719015068b06efbce41b7768429f24239 100644
(file)
--- a/
src/soc/iommu/axi_rab/ram_tp_write_first.py
+++ b/
src/soc/iommu/axi_rab/ram_tp_write_first.py
@@
-52,7
+52,7
@@
class ram_tp_write_first(Elaboratable):
self.d1_o = Signal(DATA_WIDTH) # output
DEPTH = int(math.pow(2, ADDR_WIDTH))
- self.ram = Memory(
DATA_WIDTH,
DEPTH)
+ self.ram = Memory(
width=DATA_WIDTH, depth=
DEPTH)
#
# localparam DEPTH = 2**ADDR_WIDTH;