versa_ecp5 adds ability to build and load for ulx3s85f, fixes testgpio

[soc.git] / src / soc / litex / core.py

diff --git a/src/soc/litex/core.py b/src/soc/litex/core.py
index fa73084b87bc9b7b9e4d6f04f2eaa3fef64730bb..d391eb700500ede61a3615b897230cfba3a4ecf5 100644 (file)
--- a/src/soc/litex/core.py
+++ b/src/soc/litex/core.py
@@ -9,13 +9,13 @@ from migen import ClockSignal, ResetSignal, Signal, Instance, Cat
 
 from litex import get_data_mod
 from litex.soc.interconnect import wishbone
-from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
+from litex.soc.cores.cpu import CPU
 
 CPU_VARIANTS = ["standard"]
 
 
 class LibreSOC(CPU):
-    name                 = "libre-soc"
+    name                 = "libre_soc"
     human_name           = "Libre-SOC"
     variants             = CPU_VARIANTS
     data_width           = 64
@@ -59,6 +59,7 @@ class LibreSOC(CPU):
         self.core_busy    = Signal()   # core is running (busy)
 
         # instruction and data bus: 64-bit, 48 bit addressing
+        # sigh self.ibus  = wishbone.Interface(data_width=32, adr_width=48)
         self.ibus         = wishbone.Interface(data_width=64, adr_width=48)
         self.dbus         = wishbone.Interface(data_width=64, adr_width=48)
 
@@ -85,6 +86,7 @@ class LibreSOC(CPU):
             o_ibus__cti   = self.ibus.cti,
             o_ibus__bte   = self.ibus.bte,
             o_ibus__we    = self.ibus.we,
+            # sigh o_ibus__adr   = self.ibus.adr, # for 32-bit
             o_ibus__adr   = Cat(Signal(3), self.ibus.adr), # 64-bit
             o_ibus__dat_w = self.ibus.dat_w,
             o_ibus__sel   = self.ibus.sel,
@@ -124,8 +126,9 @@ class LibreSOC(CPU):
     @staticmethod
     def elaborate(verilog_filename):
         cli_params = []
-        sdir = get_data_mod("cpu", "libre-soc").data_location
-        if subprocess.call(["python3", os.path.join(sdir, "cli.py"),
+        #sdir = get_data_mod("cpu", "libre_soc").data_location
+        sdir = "./simple"
+        if subprocess.call(["python3", os.path.join(sdir, "issuer_verilog.py"),
                             *cli_params, verilog_filename],
                             ):
             raise OSError("Unable to elaborate Libre-SOC CPU, "
@@ -134,8 +137,7 @@ class LibreSOC(CPU):
     def do_finalize(self):
         verilog_filename = os.path.join(self.platform.output_dir,
                                         "gateware", "libre-soc.v")
-        self.elaborate(
-            verilog_filename = verilog_filename)
+        self.elaborate(verilog_filename=verilog_filename)
         self.platform.add_source(verilog_filename)
         self.specials += Instance("test_issuer", **self.cpu_params)