minerva tests: Don't import soc.minerva.csr

[soc.git] / src / soc / minerva / units / debug / top.py

diff --git a/src/soc/minerva/units/debug/top.py b/src/soc/minerva/units/debug/top.py
index 588486bd479410302f5e5c73af889fccc7262c71..2b82f0d57e3934825cc2c9a0c3626b5b66727d2e 100644 (file)
--- a/src/soc/minerva/units/debug/top.py
+++ b/src/soc/minerva/units/debug/top.py
@@ -1,7 +1,6 @@
 from nmigen import Elaboratable, Module, Signal, Record
 
 
-from ...csr import AutoCSR, CSR
 from ...wishbone import wishbone_layout
 from .controller import DebugController
 from .jtag import JTAGReg, dtmcs_layout, dmi_layout, jtag_layout
@@ -28,7 +27,7 @@ jtag_regs = {
 }
 
 
-class DebugUnit(Elaboratable, AutoCSR):
+class DebugUnit(Elaboratable):
     def __init__(self):
         self.jtag = Record(jtag_layout)
         self.dbus = Record(wishbone_layout)