port minerva cache fixes

[soc.git] / src / soc / minerva / units / fetch.py

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index b7cdad11bf3528c848f2a10ce62918f6933fec5c..04e1f58d51664dad25a8e74ad1e4c4638c922e29 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -178,7 +178,7 @@ class CachedFetchUnit(FetchUnitInterface, Elaboratable):
             ]
         with m.Elif(f_icache_select):
             m.d.comb += [
-                self.f_busy_o.eq(icache.s2_re & icache.s2_miss),
+                self.f_busy_o.eq(icache.s2_miss),
                 self.f_instr_o.eq(icache.s2_rdata)
             ]
         with m.Else():