allow imem to be 64/32 bit wide

[soc.git] / src / soc / minerva / units / fetch.py

diff --git a/src/soc/minerva/units/fetch.py b/src/soc/minerva/units/fetch.py
index 74d6d8e6e002de66e8e15e780c317c054981d554..2022127592c1b5c5ee8bb30c7a7cab84983f5014 100644 (file)
--- a/src/soc/minerva/units/fetch.py
+++ b/src/soc/minerva/units/fetch.py
@@ -12,8 +12,11 @@ class FetchUnitInterface:
     def __init__(self, pspec):
         self.pspec = pspec
         self.addr_wid = pspec.addr_wid
-        self.data_wid = pspec.reg_wid
-        self.adr_lsbs = log2_int(pspec.reg_wid//8)
+        if isinstance(pspec.imem_reg_wid, int):
+            self.data_wid = pspec.imem_reg_wid
+        else:
+            self.data_wid = pspec.reg_wid
+        self.adr_lsbs = log2_int(self.data_wid//8)
         self.ibus = Record(make_wb_layout(pspec))
         bad_wid = pspec.addr_wid - self.adr_lsbs # TODO: is this correct?