minerva tests: Don't import soc.minerva.csr

[soc.git] / src / soc / minerva / wishbone.py

diff --git a/src/soc/minerva/wishbone.py b/src/soc/minerva/wishbone.py
index 1f56619fac4659a7b7c16417968079fde746470c..f84a01ccc2f3b98f57ffe16c37cb5a2c206cf24b 100644 (file)
--- a/src/soc/minerva/wishbone.py
+++ b/src/soc/minerva/wishbone.py
@@ -4,7 +4,7 @@ from nmigen.lib.coding import PriorityEncoder
 from nmigen.utils import log2_int
 
 
-__all__ = ["Cycle", "wishbone_layout", "make_wb_layout", "WishboneArbiter"]
+__all__ = ["Cycle", "make_wb_layout", "WishboneArbiter"]
 
 
 class Cycle:
@@ -14,11 +14,12 @@ class Cycle:
     END       = 7
 
 
-def make_wb_layout(addr_wid, mask_wid, data_wid):
+def make_wb_layout(spec, cti=True):
+    addr_wid, mask_wid, data_wid = spec.addr_wid, spec.mask_wid, spec.reg_wid
     adr_lsbs = log2_int(mask_wid) # LSBs of addr covered by mask
-    badwid = addr_wid-adr_lsbs    # MSBs (not covered by mask)
+    badwid = spec.addr_wid-adr_lsbs    # MSBs (not covered by mask)
 
-    return [
+    res = [
     ("adr",   badwid  , DIR_FANOUT),
     ("dat_w", data_wid, DIR_FANOUT),
     ("dat_r", data_wid, DIR_FANIN),
@@ -27,17 +28,19 @@ def make_wb_layout(addr_wid, mask_wid, data_wid):
     ("stb",           1, DIR_FANOUT),
     ("ack",           1, DIR_FANIN),
     ("we",            1, DIR_FANOUT),
-    ("cti",           3, DIR_FANOUT),
-    ("bte",           2, DIR_FANOUT),
     ("err",           1, DIR_FANIN)
     ]
-
-wishbone_layout = make_wb_layout(32, 4, 32)
+    if not cti:
+        return res
+    return res + [
+        ("cti",           3, DIR_FANOUT),
+        ("bte",           2, DIR_FANOUT),
+    ]
 
 
 class WishboneArbiter(Elaboratable):
-    def __init__(self):
-        self.bus = Record(wishbone_layout)
+    def __init__(self, pspec):
+        self.bus = Record(make_wb_layout(pspec))
         self._port_map = dict()
 
     def port(self, priority):