working on splitting out common mul pipe test code

[soc.git] / src / soc / regfile / regfile.py

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index 10b3fa0692922818d6e318b9168f014bb8e87070..30063726137032501e6838f5712d690395d91de6 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -32,8 +32,9 @@ import operator
 
 
 class Register(Elaboratable):
-    def __init__(self, width, writethru=True, synced=True):
+    def __init__(self, width, writethru=True, synced=True, resetval=0):
         self.width = width
+        self.reset = resetval
         self.writethru = writethru
         self.synced = synced
         self._rdports = []
@@ -55,7 +56,7 @@ class Register(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
-        self.reg = reg = Signal(self.width, name="reg")
+        self.reg = reg = Signal(self.width, name="reg", reset=self.reset)
 
         if self.synced:
             domain = m.d.sync