write-release moves out of "ALU valid" due to using alu_pulse

[soc.git] / src / soc / regfile / regfile.py

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index aef0a5541523cc12d704da9ecf83bde21425b118..d0a7b5402668bdaf568f68906d825a6d3f6eb291 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -68,7 +68,7 @@ class Register(Elaboratable):
                 else:
                     m.d.comb += rp.data_o.eq(reg)
 
-        # write ports, don't allow write to address 0 (ignore it)
+        # write ports, delayed by 1 cycle
         for wp in self._wrports:
             with m.If(wp.wen):
                 m.d.sync += reg.eq(wp.data_i)
@@ -84,8 +84,8 @@ class Register(Elaboratable):
     def ports(self):
         res = list(self)
 
-def ortreereduce(tree):
-    return treereduce(tree, operator.or_, lambda x: getattr(x, "data_o"))
+def ortreereduce(tree, attr="data_o"):
+    return treereduce(tree, operator.or_, lambda x: getattr(x, attr))
 
 
 class RegFileArray(Elaboratable):
@@ -203,9 +203,9 @@ class RegFile(Elaboratable):
                 with m.If(~wr_detect):
                     m.d.comb += rp.data_o.eq(regs[rp.raddr])
 
-        # write ports, don't allow write to address 0 (ignore it)
+        # write ports, delayed by one cycle
         for wp in self._wrports:
-            with m.If(wp.wen & (wp.waddr != Const(0, bsz))):
+            with m.If(wp.wen):
                 m.d.sync += regs[wp.waddr].eq(wp.data_i)
 
         return m