always set fwd_bus_mode=False on regfiles

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 1ce560e9da8cb3bd51f13ee06aa72b5ede15a1e4..28f8172d74774bdc8c0a95a4406a21520256f7d6 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -33,6 +33,7 @@ from openpower.consts import StateRegsEnum, XERRegsEnum, FastRegsEnum
 
 from nmigen import Module
 from nmigen.cli import rtlil
+from nmutil.latch import SRLatch
 
 
 def create_ports(rf, wr_spec, rd_spec):
@@ -97,7 +98,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
     * write-through capability (read on same cycle as write)
     """
     def __init__(self, svp64_en=False, regreduce_en=False):
-        super().__init__(64, 32, fwd_bus_mode=not regreduce_en)
+        super().__init__(64, 32, fwd_bus_mode=False)
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
         wr_spec, rd_spec = self.get_port_specs()
@@ -134,7 +135,7 @@ class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
     Note: r/w issue are used by issuer to increment/decrement TB/DEC.
     """
     def __init__(self, svp64_en=False, regreduce_en=False):
-        super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=not regreduce_en)
+        super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=False)
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
         wr_spec, rd_spec = self.get_port_specs()
@@ -149,6 +150,9 @@ class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
                         }
         if not self.regreduce_en:
             r_port_spec['fast2'] = "src2"
+            r_port_spec['fast3'] = "src3"
+            w_port_spec['fast2'] = "dest2"
+            w_port_spec['fast3'] = "dest3"
 
         return w_port_spec, r_port_spec
 
@@ -230,7 +234,7 @@ class SPRRegs(RegFileMem):
         else:
             n_sprs = len(SPRfull)
         super().__init__(width=64, depth=n_sprs,
-                         fwd_bus_mode=not regreduce_en)
+                         fwd_bus_mode=False)
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
         wr_spec, rd_spec = self.get_port_specs()
@@ -269,36 +273,22 @@ class RegFiles:
         self.rv, self.wv = {}, {}
         if make_hazard_vecs:
             # create a read-hazard and write-hazard vectors for this regfile
-            self.wv = make_vecs(self, "wr") # global write vectors
-            self.rv = make_vecs(self, "rd") # global read vectors
+            self.wv = self.make_vecs("wr") # global write vectors
+            self.rv = self.make_vecs("rd") # global read vectors
 
     def make_vecs(self, name):
         vec = {}
         # create regfiles here, Factory style
         for (name, kls) in RegFiles.regkls:
+            rf = self.rf[name]
             vec[name] = self.make_hazard_vec(rf, name)
         return vec
 
     def make_hazard_vec(self, rf, name):
         if isinstance(rf, VirtualRegPort):
-            vec = RegFileArray(rf.bitwidth, 1)
+            vec = SRLatch(sync=False, llen=rf.nregs, name=name)
         else:
-            vec = RegFileArray(rf.depth, 1)
-        if name in ['int', 'cr', 'xer']:
-            n_wrs = 3
-        elif name in ['fast']:
-            n_wrs = 2
-        else:
-            n_wrs = 1
-        # add write ports
-        vec.w_ports = {}
-        for i in range(n_wrs):
-            pname = "wr%d" % i
-            vec.w_ports[pname] = vec.write_port("%s_%s" % (name, pname))
-        # add read port
-        vec.r_ports = {}
-        pname = "rd%d" % 0
-        vec.r_ports[pname] = vec.read_port("%s_%s" % (name, pname))
+            vec = SRLatch(sync=False, llen=rf.depth, name=name)
         return vec
 
     def elaborate_into(self, m, platform):