always set fwd_bus_mode=False on regfiles

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 8461181a3d35866d2ff02e34ed9250cd334b6f82..28f8172d74774bdc8c0a95a4406a21520256f7d6 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -33,6 +33,7 @@ from openpower.consts import StateRegsEnum, XERRegsEnum, FastRegsEnum
 
 from nmigen import Module
 from nmigen.cli import rtlil
+from nmutil.latch import SRLatch
 
 
 def create_ports(rf, wr_spec, rd_spec):
@@ -97,7 +98,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
     * write-through capability (read on same cycle as write)
     """
     def __init__(self, svp64_en=False, regreduce_en=False):
-        super().__init__(64, 32, fwd_bus_mode=not regreduce_en)
+        super().__init__(64, 32, fwd_bus_mode=False)
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
         wr_spec, rd_spec = self.get_port_specs()
@@ -134,7 +135,7 @@ class FastRegs(RegFileMem, FastRegsEnum): #RegFileArray):
     Note: r/w issue are used by issuer to increment/decrement TB/DEC.
     """
     def __init__(self, svp64_en=False, regreduce_en=False):
-        super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=not regreduce_en)
+        super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=False)
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
         wr_spec, rd_spec = self.get_port_specs()
@@ -233,7 +234,7 @@ class SPRRegs(RegFileMem):
         else:
             n_sprs = len(SPRfull)
         super().__init__(width=64, depth=n_sprs,
-                         fwd_bus_mode=not regreduce_en)
+                         fwd_bus_mode=False)
         self.svp64_en = svp64_en
         self.regreduce_en = regreduce_en
         wr_spec, rd_spec = self.get_port_specs()
@@ -285,12 +286,9 @@ class RegFiles:
 
     def make_hazard_vec(self, rf, name):
         if isinstance(rf, VirtualRegPort):
-            vec = RegFileArray(1, rf.nregs)
+            vec = SRLatch(sync=False, llen=rf.nregs, name=name)
         else:
-            vec = RegFileArray(1, rf.depth)
-        # get read/write port specs and create bitvector ports with same names
-        wr_spec, rd_spec = rf.get_port_specs()
-        create_ports(vec, wr_spec, rd_spec)
+            vec = SRLatch(sync=False, llen=rf.depth, name=name)
         return vec
 
     def elaborate_into(self, m, platform):