from nmigen import Module
from nmigen.cli import rtlil
+from nmutil.latch import SRLatch
def create_ports(rf, wr_spec, rd_spec):
* write-through capability (read on same cycle as write)
"""
def __init__(self, svp64_en=False, regreduce_en=False):
- super().__init__(64, 32, fwd_bus_mode=not regreduce_en)
+ super().__init__(64, 32, fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
Note: r/w issue are used by issuer to increment/decrement TB/DEC.
"""
def __init__(self, svp64_en=False, regreduce_en=False):
- super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=not regreduce_en)
+ super().__init__(64, FastRegsEnum.N_REGS, fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
else:
n_sprs = len(SPRfull)
super().__init__(width=64, depth=n_sprs,
- fwd_bus_mode=not regreduce_en)
+ fwd_bus_mode=False)
self.svp64_en = svp64_en
self.regreduce_en = regreduce_en
wr_spec, rd_spec = self.get_port_specs()
def make_hazard_vec(self, rf, name):
if isinstance(rf, VirtualRegPort):
- vec = VirtualRegPort(rf.nregs, rf.nregs, wr2=True)
+ vec = SRLatch(sync=False, llen=rf.nregs, name=name)
else:
- vec = VirtualRegPort(rf.depth, rf.depth, wr2=True)
- # get read/write port specs and create bitvector ports with same names
- wr_spec, rd_spec = rf.get_port_specs()
- # ok, this is complicated/fun.
- # issue phase for checking whether to issue only needs one read port
- # however during regfile-read, the corresponding bitvector needs to
- # be *WRITTEN* to (a 1), and during regfile-write, the corresponding
- # bitvector *ALSO* needs to be wrtten (a 0). therefore we need to
- # MERGE the wr_spec and rd_spec with some appropriate name prefixes
- # to make sure they do not clash
- rd_bvspec = {'issue': 'full_rd'}
- wr_bvspec = {'set': 'full_wr', 'clr': 'full_wr2'}
- create_ports(vec, wr_bvspec, rd_bvspec)
+ vec = SRLatch(sync=False, llen=rf.depth, name=name)
return vec
def elaborate_into(self, m, platform):