add spr to fast reg converter

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 5461eec59d637bd97f664cd7ab5c3f3bfc4663d4..74c283f3e036c8c79545795a49bc15b37088af3f 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -136,8 +136,8 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = {'spr': self.write_port(name="dest")}
-        self.r_ports = {'spr': self.read_port("src")}
+        self.w_ports = {'spr1': self.write_port(name="dest")}
+        self.r_ports = {'spr1': self.read_port("src")}
 
 
 # class containing all regfiles: int, cr, xer, fast, spr