add spr to fast reg converter

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 7ed51a8a11f54cfdeefdc2157d2dbdb4ff51dc90..74c283f3e036c8c79545795a49bc15b37088af3f 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -70,13 +70,13 @@ class FastRegs(RegFileArray):
         super().__init__(64, 8)
         self.w_ports = {'nia': self.write_port("nia"),
                         'msr': self.write_port("dest2"),
-                        'spr1': self.write_port("dest3"),
-                        'spr2': self.write_port("dest4"),
+                        'fast1': self.write_port("dest3"),
+                        'fast2': self.write_port("dest4"),
                         'd_wr1': self.write_port("d_wr1")}
         self.r_ports = {'cia': self.read_port("src1"),
                         'msr': self.read_port("src2"),
-                        'spr1': self.read_port("src3"),
-                        'spr2': self.read_port("src4"),
+                        'fast1': self.read_port("src3"),
+                        'fast2': self.read_port("src4"),
                         'd_rd1': self.read_port("d_rd1")}
 
 
@@ -136,8 +136,8 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = {'spr': self.write_port(name="dest")}
-        self.r_ports = {'spr': self.read_port("src")}
+        self.w_ports = {'spr1': self.write_port(name="dest")}
+        self.r_ports = {'spr1': self.read_port("src")}
 
 
 # class containing all regfiles: int, cr, xer, fast, spr