add spr to fast reg converter

[soc.git] / src / soc / regfile / regfiles.py

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index ee9a7ff8d7d5ff2858486d5d35e5b7a8f70d93e5..74c283f3e036c8c79545795a49bc15b37088af3f 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -9,6 +9,9 @@ Defines the following register files:
     * XER regfile   - XER.so, XER.ca/ca32, XER.ov/ov32
     * FAST regfile  - PC, MSR, CTR, LR, TAR, SRR1, SRR2
 
+Note: this should NOT have name conventions hard-coded (dedicated ports per
+regname).  However it is convenient for now.
+
 Links:
 
 * https://bugs.libre-soc.org/show_bug.cgi?id=345
@@ -19,7 +22,6 @@ Links:
 
 # TODO
 
-from nmigen import Elaboratable, Module
 from soc.regfile.regfile import RegFile, RegFileArray
 from soc.regfile.virtual_port import VirtualRegPort
 from soc.decoder.power_enums import SPR
@@ -36,11 +38,11 @@ class IntRegs(RegFileArray):
     """
     def __init__(self):
         super().__init__(64, 32)
-        self.w_ports = [self.write_port("dest1"),
-                        self.write_port("dest2")] # for now (LD/ST update)
-        self.r_ports = [self.read_port("src1"),
-                        self.read_port("src2"),
-                        self.read_port("src3")]
+        self.w_ports = {'o': self.write_port("dest1"),
+                        'o1': self.write_port("dest2")} # for now (LD/ST update)
+        self.r_ports = {'ra': self.read_port("src1"),
+                        'rb': self.read_port("src2"),
+                        'rc': self.read_port("src3")}
 
 
 # Fast SPRs Regfile
@@ -53,21 +55,29 @@ class FastRegs(RegFileArray):
     * 3R2W
     * Array-based unary-indexed (not binary-indexed)
     * write-through capability (read on same cycle as write)
+
+    Note: d_wr1 and d_rd1 are for use by the decoder, to get at the PC.
+    will probably have to also add one so it can get at the MSR as well.
     """
     PC = 0
     MSR = 1
     CTR = 2
     LR = 3
     TAR = 4
-    SRR1 = 5
-    SRR2 = 6
+    SRR0 = 5
+    SRR1 = 6
     def __init__(self):
         super().__init__(64, 8)
-        self.w_ports = [self.write_port("dest1"),
-                        self.write_port("dest2")]
-        self.r_ports = [self.read_port("src1"),
-                        self.read_port("src2"),
-                        self.read_port("src3")]
+        self.w_ports = {'nia': self.write_port("nia"),
+                        'msr': self.write_port("dest2"),
+                        'fast1': self.write_port("dest3"),
+                        'fast2': self.write_port("dest4"),
+                        'd_wr1': self.write_port("d_wr1")}
+        self.r_ports = {'cia': self.read_port("src1"),
+                        'msr': self.read_port("src2"),
+                        'fast1': self.read_port("src3"),
+                        'fast2': self.read_port("src4"),
+                        'd_rd1': self.read_port("d_rd1")}
 
 
 # CR Regfile
@@ -81,12 +91,13 @@ class CRRegs(VirtualRegPort):
     """
     def __init__(self):
         super().__init__(32, 8)
-        self.w_ports = [self.full_wr, # 32-bit wide (masked, 8-en lines)
-                        self.write_port("dest")] # 4-bit wide, unary-indexed
-        self.r_ports = [self.full_rd, # 32-bit wide (masked, 8-en lines)
-                        self.read_port("src1"),
-                        self.read_port("src2"),
-                        self.read_port("src3")]
+        self.w_ports = {'full_cr': self.full_wr, # 32-bit (masked, 8-en lines)
+                        'cr_a': self.write_port("dest1"), # 4-bit, unary-indexed
+                        'cr_b': self.write_port("dest2")} # 4-bit, unary-indexed
+        self.r_ports = {'full_cr': self.full_rd, # 32-bit (masked, 8-en lines)
+                        'cr_a': self.read_port("src1"),
+                        'cr_b': self.read_port("src2"),
+                        'cr_c': self.read_port("src3")}
 
 
 # XER Regfile
@@ -102,15 +113,15 @@ class XERRegs(VirtualRegPort):
     CA=1 # CA and CA32
     OV=2 # OV and OV32
     def __init__(self):
-        super().__init__(6, 2)
-        self.w_ports = [self.full_wr, # 6-bit wide (masked, 3-en lines)
-                        self.write_port("dest1"),
-                        self.write_port("dest2"),
-                        self.write_port("dest3")]
-        self.r_ports = [self.full_rd, # 6-bit wide (masked, 3-en lines)
-                        self.read_port("src1"),
-                        self.read_port("src2"),
-                        self.read_port("src3")]
+        super().__init__(6, 3)
+        self.w_ports = {'full_xer': self.full_wr, # 6-bit (masked, 3-en lines)
+                        'xer_so': self.write_port("dest1"),
+                        'xer_ca': self.write_port("dest2"),
+                        'xer_ov': self.write_port("dest3")}
+        self.r_ports = {'full_xer': self.full_rd, # 6-bit (masked, 3-en lines)
+                        'xer_so': self.read_port("src1"),
+                        'xer_ca': self.read_port("src2"),
+                        'xer_ov': self.read_port("src3")}
 
 
 # SPR Regfile
@@ -125,23 +136,23 @@ class SPRRegs(RegFile):
     def __init__(self):
         n_sprs = len(SPR)
         super().__init__(64, n_sprs)
-        self.w_ports = [self.write_port("dest")]
-        self.r_ports = [self.read_port("src")]
+        self.w_ports = {'spr1': self.write_port(name="dest")}
+        self.r_ports = {'spr1': self.read_port("src")}
+
 
 # class containing all regfiles: int, cr, xer, fast, spr
-class RegFiles(Elaboratable):
+class RegFiles:
     def __init__(self):
         self.rf = {}
         for (name, kls) in [('int', IntRegs),
                             ('cr', CRRegs),
                             ('xer', XERRegs),
-                            ('fasr', FastRegs),
+                            ('fast', FastRegs),
                             ('spr', SPRRegs),]:
             rf = self.rf[name] = kls()
             setattr(self, name, rf)
 
-    def elaborate(self, platform):
-        m = Module()
+    def elaborate_into(self, m, platform):
         for (name, rf) in self.rf.items():
             setattr(m.submodules, name, rf)
         return m