adding in ALU test back in, debugging SPR setup

[soc.git] / src / soc / regfile / util.py

diff --git a/src/soc/regfile/util.py b/src/soc/regfile/util.py
index dff63be8da15d7f6ebe77f2285e7f1415a0c0e1b..536c16fbfb53a6b2a4bb7269c5ae001dc2745dbf 100644 (file)
--- a/src/soc/regfile/util.py
+++ b/src/soc/regfile/util.py
@@ -1,5 +1,5 @@
 from soc.regfile.regfiles import FastRegs
-from soc.decoder.power_enums import SPR
+from soc.decoder.power_enums import SPR, spr_dict
 
 def fast_reg_to_spr(spr_num):
     if spr_num == FastRegs.CTR: