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sort out SPR setting in MMU
[soc.git]
/
src
/
soc
/
regfile
/
util.py
diff --git
a/src/soc/regfile/util.py
b/src/soc/regfile/util.py
index 79effa7c251d589d045478a7f6e16ab095fafd21..5ccc4c54c607d1c6cc18f4d0fbd672353d8646d7 100644
(file)
--- a/
src/soc/regfile/util.py
+++ b/
src/soc/regfile/util.py
@@
-24,7
+24,7
@@
def fast_reg_to_spr(spr_num):
def spr_to_fast_reg(spr_num):
if not isinstance(spr_num, str):
spr_num = spr_dict[spr_num].SPR
- return sprstr_to_fast
[spr_num]
+ return sprstr_to_fast
.get(spr_num, None)
def slow_reg_to_spr(slow_reg):