add CR read to DMI interface

[soc.git] / src / soc / regfile / virtual_port.py

diff --git a/src/soc/regfile/virtual_port.py b/src/soc/regfile/virtual_port.py
index ec1ee2c33edfadc10f6785d81d3626a4744e4e2e..f4393e152d2030de442cc124deca0e707adc7bfb 100644 (file)
--- a/src/soc/regfile/virtual_port.py
+++ b/src/soc/regfile/virtual_port.py
@@ -18,9 +18,10 @@ from soc.regfile.regfile import RegFileArray
 
 
 class VirtualRegPort(RegFileArray):
-    def __init__(self, bitwidth, n_regs):
+    def __init__(self, bitwidth, n_regs, rd2=False):
         self.bitwidth = bitwidth
         self.nregs = n_regs
+        self.rd2 = rd2 # eurgh hack
         self.regwidth = regwidth = bitwidth // n_regs
         super().__init__(self.regwidth, n_regs)
 
@@ -31,17 +32,15 @@ class VirtualRegPort(RegFileArray):
         self.full_rd = RecordObject([("ren", n_regs),
                                      ("data_o", bitwidth)],  # *full* wid
                                     name="full_rd")
+        if not rd2:
+            return
+        self.full_rd2 = RecordObject([("ren", n_regs),
+                                     ("data_o", bitwidth)],  # *full* wid
+                                    name="full_rd2")
 
-    def elaborate(self, platform):
-        m = super().elaborate(platform)
+    def connect_full_rd(self, m, rfull, name):
         comb = m.d.comb
-
-        # for internal use only.
-        wr_regs = self.write_reg_port(f"w")
-        rd_regs = self.read_reg_port(f"r")
-
-        # connect up full read port
-        rfull = self.full_rd
+        rd_regs = self.read_reg_port(name)
 
         # wire up the enable signals and chain-accumulate the data
         l = map(lambda port: port.data_o, rd_regs)  # get port data(s)
@@ -50,6 +49,18 @@ class VirtualRegPort(RegFileArray):
         comb += rfull.data_o.eq(Cat(*l))  # we like Cat on lists
         comb += Cat(*le).eq(rfull.ren)
 
+    def elaborate(self, platform):
+        m = super().elaborate(platform)
+        comb = m.d.comb
+
+        # for internal use only.
+        wr_regs = self.write_reg_port(f"w")
+
+        # connect up full read port
+        self.connect_full_rd(m, self.full_rd, "r")
+        if self.rd2: # hack!
+            self.connect_full_rd(m, self.full_rd2, "r2")
+
         # connect up full write port
         wfull = self.full_wr