initial version of L0CacheBuffer2

[soc.git] / src / soc / scoreboard / addr_split.py

diff --git a/src/soc/scoreboard/addr_split.py b/src/soc/scoreboard/addr_split.py
index b3156595300170a9692837809b2b150301c19360..4a9573382cdcf5bbb280a9450e4591ca8df8c795 100644 (file)
--- a/src/soc/scoreboard/addr_split.py
+++ b/src/soc/scoreboard/addr_split.py
@@ -69,18 +69,21 @@ def byteExpand(signal):
     lst = []
     for i in range(len(signal)):
         bit = signal[i]
-        for j in range(8):
+        for j in range(8): #TODO this can be optimized
             lst += [bit]
     return Cat(*lst)
 
 class LDSTSplitter(Elaboratable):
 
-    def __init__(self, dwidth, awidth, dlen):
+    def __init__(self, dwidth, awidth, dlen, pi=None):
         self.dwidth, self.awidth, self.dlen = dwidth, awidth, dlen
         # cline_wid = 8<<dlen # cache line width: bytes (8) times (2^^dlen)
         cline_wid = dwidth*8  # convert bytes to bits
 
-        self.pi =  PortInterface()
+        if(pi is None):
+            self.pi = PortInterface()
+        else:
+            self.pi = pi
 
         self.addr_i = self.pi.addr.data  #Signal(awidth, reset_less=True)
         # no match in PortInterface