test SVP64 major opcode, start checking if it is EXT001 soon

[soc.git] / src / soc / scoreboard / fu_reg_matrix.py

diff --git a/src/soc/scoreboard/fu_reg_matrix.py b/src/soc/scoreboard/fu_reg_matrix.py
index 8ca1494edc3550d3b54b8f65371837f47fae7813..06380434c8d7d20828d80c3d0e020161bcb2c2e4 100644 (file)
--- a/src/soc/scoreboard/fu_reg_matrix.py
+++ b/src/soc/scoreboard/fu_reg_matrix.py
@@ -2,10 +2,10 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl
 
-from scoreboard.dependence_cell import DependencyRow
-from scoreboard.fu_wr_pending import FU_RW_Pend
-from scoreboard.reg_select import Reg_Rsv
-from scoreboard.global_pending import GlobalPending
+from soc.scoreboard.dependence_cell import DependencyRow
+from soc.scoreboard.fu_wr_pending import FU_RW_Pend
+from soc.scoreboard.reg_select import Reg_Rsv
+from soc.scoreboard.global_pending import GlobalPending
 
 """