add twin partial address mapper class

[soc.git] / src / soc / scoreboard / memfu.py

diff --git a/src/soc/scoreboard/memfu.py b/src/soc/scoreboard/memfu.py
index 2989c8e0e3913ab7c6447ed548a7272af9cb722c..553ebb5e37c95bc7e05c6022b7252261f7fae507 100644 (file)
--- a/src/soc/scoreboard/memfu.py
+++ b/src/soc/scoreboard/memfu.py
@@ -33,7 +33,7 @@ class MemFunctionUnits(Elaboratable):
         # address matching
         self.addrs_i = Array(Signal(self.bitwid, name="addrs_i%d" % i) \
                              for i in range(n_ldsts))
-        self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address
+        #self.addr_we_i = Signal(n_ldsts) # write-enable for incoming address
         self.addr_en_i = Signal(n_ldsts) # address latched in
         self.addr_rs_i = Signal(n_ldsts) # address deactivated
 
@@ -93,7 +93,7 @@ class MemFunctionUnits(Elaboratable):
         # connect address matching: these get connected to the Addr CUs
         for i in range(self.n_ldsts):
             comb += intregdeps.addrs_i[i].eq(self.addrs_i[i])
-        comb += intregdeps.addr_we_i.eq(self.addr_we_i)
+        #comb += intregdeps.addr_we_i.eq(self.addr_we_i)
         comb += intregdeps.addr_en_i.eq(self.addr_en_i)
         comb += intregdeps.addr_rs_i.eq(self.addr_rs_i)
 
@@ -113,7 +113,7 @@ class MemFunctionUnits(Elaboratable):
         yield self.go_die_i
         yield self.fn_issue_i
         yield from self.addrs_i
-        yield self.addr_we_i
+        #yield self.addr_we_i
         yield self.addr_en_i
 
     def ports(self):