fix up Logical pipeline to produce HDL with XLEN=32

[soc.git] / src / soc / scoremulti / reg_sel.py

diff --git a/src/soc/scoremulti/reg_sel.py b/src/soc/scoremulti/reg_sel.py
index 9d36f3beeaa38da0c86290bc0a42e9e5e47bc897..46b27be73d2d60c9846aa78e54a2849b9e88c0e9 100644 (file)
--- a/src/soc/scoremulti/reg_sel.py
+++ b/src/soc/scoremulti/reg_sel.py
@@ -9,7 +9,6 @@ class Reg_Rsv(Elaboratable):
         self.n_src = n_src
         self.n_dest = n_dest
         self.fu_count = fu_count
-        self.dest_rsel_i = Signal(fu_count, reset_less=True)
         self.dest_rsel_i = Array(Signal(fu_count, name="dst_rsel_i",
                                        reset_less=True) \
                                 for i in range(n_dest))