local variable rename in FetchFSM

[soc.git] / src / soc / simple / core_data.py

diff --git a/src/soc/simple/core_data.py b/src/soc/simple/core_data.py
index 325502dd637fcdcbb454b9c4765303df71ebd66c..109fa8520c4c7e59b3c6c80b7442d0f4f6a78b01 100644 (file)
--- a/src/soc/simple/core_data.py
+++ b/src/soc/simple/core_data.py
@@ -33,9 +33,10 @@ class FetchOutput:
         self.bigendian_i = Signal() # bigendian - TODO, set by MSR.BE
 
     def eq(self, i):
-        self.state.eq(i.state)
-        self.raw_insn_i.eq(i.raw_insn_i)
-        self.bigendian_i.eq(i.bigendian_i)
+        return [self.state.eq(i.state),
+                self.raw_insn_i.eq(i.raw_insn_i),
+                self.bigendian_i.eq(i.bigendian_i),
+               ]
 
 
 class CoreInput:
@@ -77,30 +78,36 @@ class CoreInput:
             self.sv_pred_dm = Signal() # TODO: SIMD width
 
     def eq(self, i):
-        self.e.eq(i.e)
-        self.sv_a_nz.eq(i.sv_a_nz)
-        self.state.eq(i.state)
-        self.raw_insn_i.eq(i.raw_insn_i)
-        self.bigendian_i.eq(i.bigendian_i)
+        res = [self.e.eq(i.e),
+                self.sv_a_nz.eq(i.sv_a_nz),
+                self.state.eq(i.state),
+                self.raw_insn_i.eq(i.raw_insn_i),
+                self.bigendian_i.eq(i.bigendian_i),
+               ]
         if not self.svp64_en:
-            return
-        self.sv_rm.eq(i.sv_rm)
-        self.is_svp64_mode.eq(i.is_svp64_mode)
-        self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec)
-        self.sv_pred_sm.eq(i.sv_pred_sm)
-        self.sv_pred_dm.eq(i.sv_pred_dm)
+            return res
+        res += [ self.sv_rm.eq(i.sv_rm),
+                self.is_svp64_mode.eq(i.is_svp64_mode),
+                self.use_svp64_ldst_dec.eq(i.use_svp64_ldst_dec),
+                self.sv_pred_sm.eq(i.sv_pred_sm),
+                self.sv_pred_dm.eq(i.sv_pred_dm),
+                ]
+        return res
 
 
 class CoreOutput:
     def __init__(self):
         # start/stop and terminated signalling
         self.core_terminate_o = Signal()  # indicates stopped
-        self.busy_o = Signal(name="corebusy_o")  # at least one ALU busy
+        self.busy_o = Signal(name="corebusy_o")  # ALU is busy, no input
+        self.any_busy_o = Signal(name="any_busy_o")  # at least one ALU busy
         self.exc_happened = Signal()             # exception happened
 
     def eq(self, i):
-        self.core_terminate_o.eq(i.core_terminate_o)
-        self.busy_o.eq(i.busy_o)
-        self.exc_happened.eq(i.exc_happened)
+        return [self.core_terminate_o.eq(i.core_terminate_o),
+                self.busy_o.eq(i.busy_o),
+                self.any_busy_o.eq(i.any_busy_o),
+                self.exc_happened.eq(i.exc_happened),
+               ]