# not SVP64 - 32-bit only
sync += nia.eq(cur_state.pc + 4)
sync += dec_opcode_o.eq(insn)
- m.next = "INSN_READY"
+ m.next = "INSN_READY"
with m.State("INSN_READY"):
# hand over the instruction, to be decoded
nia = Signal(64)
# connect up debug signals
- comb += dbg.terminate_i.eq(core.o.core_terminate_o)
+ with m.If(core.o.core_terminate_o):
+ comb += dbg.terminate_i.eq(1)
# there are *THREE^WFOUR-if-SVP64-enabled* FSMs, fetch (32/64-bit)
# issue, decode/execute, now joined by "Predicate fetch/calculate".