from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
-from soc.clock.select import ClockSelect, DummyPLL
+from soc.clock.select import ClockSelect
+from soc.clock.dummypll import DummyPLL
from nmutil.util import rising_edge
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
- # power-on reset delay
+ # power-on reset delay
core_rst = ResetSignal("coresync")
comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
comb += core_rst.eq(ti_rst)
insn_type = core.e.do.insn_type
+ # handshake signals between fetch and decode/execute
+ # fetch FSM can run as soon as the PC is valid
+ fetch_pc_valid_i = Signal()
+ fetch_pc_ready_o = Signal()
+ # when done, deliver the instruction to the next FSM
+ fetch_insn_o = Signal(32, reset_less=True)
+ fetch_insn_valid_o = Signal()
+ fetch_insn_ready_i = Signal()
+
# actually use a nmigen FSM for the first time (w00t)
# this FSM is perhaps unusual in that it detects conditions
# then "holds" information, combinatorially, for the core
# (as opposed to using sync - which would be on a clock's delay)
# this includes the actual opcode, valid flags and so on.
- with m.FSM() as fsm:
+ with m.FSM(name='fetch_fsm'):
# waiting (zzz)
with m.State("IDLE"):
- sync += pc_changed.eq(0)
- sync += core.e.eq(0)
- sync += core.raw_insn_i.eq(0)
- sync += core.bigendian_i.eq(0)
with m.If(~dbg.core_stop_o & ~core_rst):
- # instruction allowed to go: start by reading the PC
- # capture the PC and also drop it into Insn Memory
- # we have joined a pair of combinatorial memory
- # lookups together. this is Generally Bad.
- comb += self.imem.a_pc_i.eq(pc)
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- sync += cur_state.pc.eq(pc)
-
- # initiate read of MSR. arrives one clock later
- comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
- sync += msr_read.eq(0)
-
- m.next = "INSN_READ" # move to "wait for bus" phase
+ comb += fetch_pc_ready_o.eq(1)
+ with m.If(fetch_pc_valid_i):
+ # instruction allowed to go: start by reading the PC
+ # capture the PC and also drop it into Insn Memory
+ # we have joined a pair of combinatorial memory
+ # lookups together. this is Generally Bad.
+ comb += self.imem.a_pc_i.eq(pc)
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ sync += cur_state.pc.eq(pc)
+
+ # initiate read of MSR. arrives one clock later
+ comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
+ sync += msr_read.eq(0)
+
+ m.next = "INSN_READ" # move to "wait for bus" phase
with m.Else():
comb += core.core_stopped_i.eq(1)
comb += dbg.core_stopped_i.eq(1)
insn = f_instr_o
else:
insn = f_instr_o.word_select(cur_state.pc[2], 32)
- comb += dec_opcode_i.eq(insn) # actual opcode
+ # capture and hold the instruction from memory
+ sync += fetch_insn_o.eq(insn)
+ m.next = "INSN_READY"
+
+ with m.State("INSN_READY"):
+ # hand over the instruction, to be decoded
+ comb += fetch_insn_valid_o.eq(1)
+ with m.If(fetch_insn_ready_i):
+ m.next = "IDLE"
+
+ # decode / issue / execute FSM
+ with m.FSM():
+
+ # go fetch the instruction at the current PC
+ # at this point, there is no instruction running, that
+ # could inadvertently update the PC.
+ with m.State("INSN_FETCH"):
+ comb += fetch_pc_valid_i.eq(1)
+ with m.If(fetch_pc_ready_o):
+ m.next = "INSN_WAIT"
+
+ # decode the instruction when it arrives
+ with m.State("INSN_WAIT"):
+ comb += fetch_insn_ready_i.eq(1)
+ with m.If(fetch_insn_valid_o):
+ # decode the instruction
+ comb += dec_opcode_i.eq(fetch_insn_o) # actual opcode
sync += core.e.eq(pdecode2.e)
sync += core.state.eq(cur_state)
sync += core.raw_insn_i.eq(dec_opcode_i)
with m.State("INSN_START"):
comb += core_ivalid_i.eq(1) # instruction is valid
comb += core_issue_i.eq(1) # and issued
+ sync += pc_changed.eq(0)
m.next = "INSN_ACTIVE" # move to "wait completion"
sync += core.e.eq(0)
sync += core.raw_insn_i.eq(0)
sync += core.bigendian_i.eq(0)
- m.next = "IDLE" # back to idle
+ m.next = "INSN_FETCH" # back to fetch
# this bit doesn't have to be in the FSM: connect up to read
# regfiles on demand from DMI
self.ti = TestIssuerInternal(pspec)
self.pll = DummyPLL()
- self.clksel = ClockSelect()
# PLL direct clock or not
self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
+ if self.pll_en:
+ self.pll_18_o = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
m.submodules.ti = ti = self.ti
cd_int = ClockDomain("coresync")
- # ClockSelect runs at PLL output internal clock rate
- m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
- m.submodules.pll = pll = self.pll
+ if self.pll_en:
+ # ClockSelect runs at PLL output internal clock rate
+ m.submodules.pll = pll = self.pll
+
+ # add clock domains from PLL
+ cd_pll = ClockDomain("pllclk")
+ m.domains += cd_pll
+
+ # PLL clock established. has the side-effect of running clklsel
+ # at the PLL's speed (see DomainRenamer("pllclk") above)
+ pllclk = ClockSignal("pllclk")
+ comb += pllclk.eq(pll.clk_pll_o)
+
+ # wire up external 24mhz to PLL
+ comb += pll.clk_24_i.eq(ClockSignal())
+
+ # output 18 mhz PLL test signal
+ comb += self.pll_18_o.eq(pll.pll_18_o)
- # add 2 clock domains established above...
- cd_pll = ClockDomain("pllclk")
- m.domains += cd_pll
+ # now wire up ResetSignals. don't mind them being in this domain
+ pll_rst = ResetSignal("pllclk")
+ comb += pll_rst.eq(ResetSignal())
# internal clock is set to selector clock-out. has the side-effect of
# running TestIssuer at this speed (see DomainRenamer("intclk") above)
intclk = ClockSignal("coresync")
if self.pll_en:
- comb += intclk.eq(clksel.core_clk_o)
+ comb += intclk.eq(pll.clk_pll_o)
else:
comb += intclk.eq(ClockSignal())
- # PLL clock established. has the side-effect of running clklsel
- # at the PLL's speed (see DomainRenamer("pllclk") above)
- pllclk = ClockSignal("pllclk")
- comb += pllclk.eq(pll.clk_pll_o)
-
- # wire up external 24mhz to PLL and clksel
- comb += clksel.clk_24_i.eq(ClockSignal())
- comb += pll.clk_24_i.eq(clksel.clk_24_i)
-
- # now wire up ResetSignals. don't mind them all being in this domain
- #int_rst = ResetSignal("coresync")
- pll_rst = ResetSignal("pllclk")
- #comb += int_rst.eq(ResetSignal())
- comb += pll_rst.eq(ResetSignal())
-
return m
def ports(self):
return list(self.ti.ports()) + list(self.pll.ports()) + \
- [ClockSignal(), ResetSignal()] + \
- list(self.clksel.ports())
+ [ClockSignal(), ResetSignal()]
def external_ports(self):
ports = self.ti.external_ports()
ports.append(ClockSignal())
ports.append(ResetSignal())
- ports.append(self.clksel.clk_sel_i)
- ports.append(self.clksel.pll_48_o)
+ if self.pll_en:
+ ports.append(self.pll.clk_sel_i)
+ ports.append(self.pll_18_o)
+ ports.append(self.pll.pll_lck_o)
return ports
projects / soc.git / blobdiff