from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
-from soc.clock.select import ClockSelect, DummyPLL
+from soc.clock.select import ClockSelect
+from soc.clock.dummypll import DummyPLL
from nmutil.util import rising_edge
"""
def __init__(self, pspec):
+ # JTAG interface. add this right at the start because if it's
+ # added it *modifies* the pspec, by adding enable/disable signals
+ # for parts of the rest of the core
+ self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
+ if self.jtag_en:
+ subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
+ 'pwm', 'sd0', 'sdr'}
+ self.jtag = JTAG(get_pinspecs(subset=subset))
+ # add signals to pspec to enable/disable icache and dcache
+ # (or data and intstruction wishbone if icache/dcache not included)
+ # https://bugs.libre-soc.org/show_bug.cgi?id=520
+ # TODO: do we actually care if these are not domain-synchronised?
+ # honestly probably not.
+ pspec.wb_icache_en = self.jtag.wb_icache_en
+ pspec.wb_dcache_en = self.jtag.wb_dcache_en
+
# add interrupt controller?
self.xics = hasattr(pspec, "xics") and pspec.xics == True
if self.xics:
# DMI interface
self.dbg = CoreDebug()
- # JTAG interface
- self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
- if self.jtag_en:
- subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
- 'pwm', 'sd0'}#, 'sdr'}
- self.jtag = JTAG(get_pinspecs(subset=subset))
-
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
m.submodules.simple_gpio = simple_gpio = self.simple_gpio
# connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
- if self.gpio and self.xics:
- comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
+ # XXX causes litex ECP5 test to get wrong idea about input and output
+ # (but works with verilator sim *sigh*)
+ #if self.gpio and self.xics:
+ # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
# instruction decoder
pdecode = create_pdecode()
core_sync = ClockDomain("coresync")
m.domains += cd_por, cd_sync, core_sync
+ ti_rst = Signal(reset_less=True)
delay = Signal(range(4), reset=3)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
comb += cd_por.clk.eq(ClockSignal())
- comb += core_sync.clk.eq(ClockSignal())
- # power-on reset delay
- comb += core.core_reset_i.eq(delay != 0 | dbg.core_rst_o)
+
+ # power-on reset delay
+ core_rst = ResetSignal("coresync")
+ comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
+ comb += core_rst.eq(ti_rst)
# busy/halted signals from core
comb += self.busy_o.eq(core.busy_o)
insn_type = core.e.do.insn_type
+ # handshake signals between fetch and decode/execute
+ # fetch FSM can run as soon as the PC is valid
+ fetch_pc_valid_i = Signal()
+ fetch_pc_ready_o = Signal()
+ # when done, deliver the instruction to the next FSM
+ fetch_insn_o = Signal(32, reset_less=True)
+ fetch_insn_valid_o = Signal()
+ fetch_insn_ready_i = Signal()
+
# actually use a nmigen FSM for the first time (w00t)
# this FSM is perhaps unusual in that it detects conditions
# then "holds" information, combinatorially, for the core
# (as opposed to using sync - which would be on a clock's delay)
# this includes the actual opcode, valid flags and so on.
- with m.FSM() as fsm:
+ with m.FSM(name='fetch_fsm'):
# waiting (zzz)
with m.State("IDLE"):
- sync += pc_changed.eq(0)
- sync += core.e.eq(0)
- sync += core.raw_insn_i.eq(0)
- sync += core.bigendian_i.eq(0)
- with m.If(~dbg.core_stop_o & ~core.core_reset_i):
- # instruction allowed to go: start by reading the PC
- # capture the PC and also drop it into Insn Memory
- # we have joined a pair of combinatorial memory
- # lookups together. this is Generally Bad.
- comb += self.imem.a_pc_i.eq(pc)
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- sync += cur_state.pc.eq(pc)
-
- # initiate read of MSR. arrives one clock later
- comb += self.state_r_msr.ren.eq(1<<StateRegs.MSR)
- sync += msr_read.eq(0)
-
- m.next = "INSN_READ" # move to "wait for bus" phase
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ comb += fetch_pc_ready_o.eq(1)
+ with m.If(fetch_pc_valid_i):
+ # instruction allowed to go: start by reading the PC
+ # capture the PC and also drop it into Insn Memory
+ # we have joined a pair of combinatorial memory
+ # lookups together. this is Generally Bad.
+ comb += self.imem.a_pc_i.eq(pc)
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ sync += cur_state.pc.eq(pc)
+
+ # initiate read of MSR. arrives one clock later
+ comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
+ sync += msr_read.eq(0)
+
+ m.next = "INSN_READ" # move to "wait for bus" phase
with m.Else():
comb += core.core_stopped_i.eq(1)
comb += dbg.core_stopped_i.eq(1)
insn = f_instr_o
else:
insn = f_instr_o.word_select(cur_state.pc[2], 32)
- comb += dec_opcode_i.eq(insn) # actual opcode
+ # capture and hold the instruction from memory
+ sync += fetch_insn_o.eq(insn)
+ m.next = "INSN_READY"
+
+ with m.State("INSN_READY"):
+ # hand over the instruction, to be decoded
+ comb += fetch_insn_valid_o.eq(1)
+ with m.If(fetch_insn_ready_i):
+ m.next = "IDLE"
+
+ # decode / issue / execute FSM
+ with m.FSM():
+
+ # go fetch the instruction at the current PC
+ # at this point, there is no instruction running, that
+ # could inadvertently update the PC.
+ with m.State("INSN_FETCH"):
+ comb += fetch_pc_valid_i.eq(1)
+ with m.If(fetch_pc_ready_o):
+ m.next = "INSN_WAIT"
+
+ # decode the instruction when it arrives
+ with m.State("INSN_WAIT"):
+ comb += fetch_insn_ready_i.eq(1)
+ with m.If(fetch_insn_valid_o):
+ # decode the instruction
+ comb += dec_opcode_i.eq(fetch_insn_o) # actual opcode
sync += core.e.eq(pdecode2.e)
sync += core.state.eq(cur_state)
sync += core.raw_insn_i.eq(dec_opcode_i)
with m.State("INSN_START"):
comb += core_ivalid_i.eq(1) # instruction is valid
comb += core_issue_i.eq(1) # and issued
+ sync += pc_changed.eq(0)
m.next = "INSN_ACTIVE" # move to "wait completion"
sync += core.e.eq(0)
sync += core.raw_insn_i.eq(0)
sync += core.bigendian_i.eq(0)
- m.next = "IDLE" # back to idle
+ m.next = "INSN_FETCH" # back to fetch
# this bit doesn't have to be in the FSM: connect up to read
# regfiles on demand from DMI
class TestIssuer(Elaboratable):
def __init__(self, pspec):
self.ti = TestIssuerInternal(pspec)
+
self.pll = DummyPLL()
- self.clksel = ClockSelect()
+
+ # PLL direct clock or not
+ self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
+ if self.pll_en:
+ self.pll_18_o = Signal(reset_less=True)
def elaborate(self, platform):
m = Module()
comb = m.d.comb
- # TestIssuer runs at internal clock rate
- m.submodules.ti = ti = DomainRenamer("intclk")(self.ti)
- # ClockSelect runs at PLL output internal clock rate
- m.submodules.clksel = clksel = DomainRenamer("pllclk")(self.clksel)
- m.submodules.pll = pll = self.pll
+ # TestIssuer runs at direct clock
+ m.submodules.ti = ti = self.ti
+ cd_int = ClockDomain("coresync")
- # add 2 clock domains established above...
- cd_int = ClockDomain("intclk")
- cd_pll = ClockDomain("pllclk")
- # probably don't have to add cd_int because of DomainRenamer("coresync")
- m.domains += cd_pll
+ if self.pll_en:
+ # ClockSelect runs at PLL output internal clock rate
+ m.submodules.pll = pll = self.pll
- # internal clock is set to selector clock-out. has the side-effect of
- # running TestIssuer at this speed (see DomainRenamer("intclk") above)
- comb += cd_int.clk.eq(clksel.core_clk_o)
+ # add clock domains from PLL
+ cd_pll = ClockDomain("pllclk")
+ m.domains += cd_pll
+
+ # PLL clock established. has the side-effect of running clklsel
+ # at the PLL's speed (see DomainRenamer("pllclk") above)
+ pllclk = ClockSignal("pllclk")
+ comb += pllclk.eq(pll.clk_pll_o)
+
+ # wire up external 24mhz to PLL
+ comb += pll.clk_24_i.eq(ClockSignal())
- # PLL clock established. has the side-effect of running clklsel
- # at the PLL's speed (see DomainRenamer("pllclk") above)
- comb += cd_pll.clk.eq(pll.clk_pll_o)
+ # output 18 mhz PLL test signal
+ comb += self.pll_18_o.eq(pll.pll_18_o)
- # wire up external 24mhz to PLL and clksel
- comb += clksel.clk_24_i.eq(ClockSignal())
- comb += pll.clk_24_i.eq(clksel.clk_24_i)
+ # now wire up ResetSignals. don't mind them being in this domain
+ pll_rst = ResetSignal("pllclk")
+ comb += pll_rst.eq(ResetSignal())
- # now wire up ResetSignals. don't mind them all being in this domain
- comb += pll.rst.eq(ResetSignal())
- comb += clksel.rst.eq(ResetSignal())
+ # internal clock is set to selector clock-out. has the side-effect of
+ # running TestIssuer at this speed (see DomainRenamer("intclk") above)
+ intclk = ClockSignal("coresync")
+ if self.pll_en:
+ comb += intclk.eq(pll.clk_pll_o)
+ else:
+ comb += intclk.eq(ClockSignal())
return m
def ports(self):
return list(self.ti.ports()) + list(self.pll.ports()) + \
- [ClockSignal(), ResetSignal()] + \
- list(self.clksel.ports())
+ [ClockSignal(), ResetSignal()]
def external_ports(self):
ports = self.ti.external_ports()
- #ports.append(ClockSignal())
- #ports.append(ResetSignal())
- ports.append(self.clksel.clk_sel_i)
- ports.append(self.clksel.pll_48_o)
+ ports.append(ClockSignal())
+ ports.append(ResetSignal())
+ if self.pll_en:
+ ports.append(self.pll.clk_sel_i)
+ ports.append(self.pll_18_o)
+ ports.append(self.pll.pll_lck_o)
return ports
projects / soc.git / blobdiff