add quick demo/test of reading DMI reg 9

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index bf91c9bbc3fd6322af5847be988caf8f25918f80..5efc0e0ee54ba3e5cc3192774746440b68d46db0 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -49,7 +49,6 @@ class TestIssuer(Elaboratable):
 
         # DMI interface
         self.dbg = CoreDebug()
-        self.dmi = self.dbg.dmi
 
         # instruction go/monitor
         self.pc_o = Signal(64, reset_less=True)
@@ -63,6 +62,9 @@ class TestIssuer(Elaboratable):
         self.fast_w_pc = self.core.regs.rf['fast'].w_ports['d_wr1'] # PC wr
         self.fast_r_msr = self.core.regs.rf['fast'].r_ports['msr'] # MSR rd
 
+        # DMI interface access
+        self.int_r = self.core.regs.rf['int'].r_ports['dmi'] # INT read
+
         # hack method of keeping an eye on whether branch/trap set the PC
         self.fast_nia = self.core.regs.rf['fast'].w_ports['nia']
         self.fast_nia.wen.name = 'fast_nia_wen'
@@ -75,6 +77,10 @@ class TestIssuer(Elaboratable):
         m.submodules.imem = imem = self.imem
         m.submodules.dbg = dbg = self.dbg
 
+        # convenience
+        dmi = dbg.dmi
+        d_reg = dbg.dbg_gpr
+
         # clock delay power-on reset
         cd_por  = ClockDomain(reset_less=True)
         cd_sync = ClockDomain()
@@ -209,6 +215,16 @@ class TestIssuer(Elaboratable):
                         comb += self.fast_w_pc.data_i.eq(nia)
                     m.next = "IDLE" # back to idle
 
+        # this bit doesn't have to be in the FSM: connect up to read
+        # regfiles on demand from DMI
+
+        with m.If(d_reg.req): # request for regfile access being made
+            # TODO: error-check this
+            # XXX should this be combinatorial?  sync better?
+            comb += self.int_r.ren.eq(1<<d_reg.addr)
+            comb += d_reg.data.eq(self.int_r.data_o)
+            comb += d_reg.ack.eq(1)
+
         return m
 
     def __iter__(self):