Re-enable core stopped signal when stopped.

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 15642018b0e459836ae809e24ed1edc96a189af8..6da1610ce25a487d4014287d8dfb76ae12b51122 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -713,13 +713,15 @@ class FetchFSM(ControlBase):
         # set priv / virt mode on I-Cache, sigh
         if isinstance(self.imem, ICache):
             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
-            comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR])
+            comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
 
         with m.FSM(name='fetch_fsm'):
 
             # waiting (zzz)
             with m.State("IDLE"):
-                with m.If(~dbg.stopping_o & ~fetch_failed & ~dbg.core_stop_o):
+                # fetch allowed if not failed and stopped but not stepping
+                # (see dmi.py for how core_stop_o is generated)
+                with m.If(~fetch_failed & ~dbg.core_stop_o):
                     comb += fetch_pc_o_ready.eq(1)
                 with m.If(fetch_pc_i_valid & ~pdecode2.instr_fault
                           & ~dbg.core_stop_o):
@@ -739,10 +741,11 @@ class FetchFSM(ControlBase):
 
             # dummy pause to find out why simulation is not keeping up
             with m.State("INSN_READ"):
-                if self.allow_overlap:
-                    stopping = dbg.stopping_o
-                else:
-                    stopping = Const(0)
+                # when using "single-step" mode, checking dbg.stopping_o
+                # prevents progress.  allow fetch to proceed once started
+                stopping = Const(0)
+                #if self.allow_overlap:
+                #    stopping = dbg.stopping_o
                 with m.If(stopping):
                     # stopping: jump back to idle
                     m.next = "IDLE"
@@ -750,6 +753,7 @@ class FetchFSM(ControlBase):
                     with m.If(self.imem.f_busy_o &
                               ~pdecode2.instr_fault):  # zzz...
                         # busy but not fetch failed: stay in wait-read
+                        comb += self.imem.a_pc_i.eq(pc)
                         comb += self.imem.a_i_valid.eq(1)
                         comb += self.imem.f_i_valid.eq(1)
                     with m.Else():
@@ -1093,10 +1097,11 @@ class TestIssuerInternal(TestIssuerBase):
 
             # wait for an instruction to arrive from Fetch
             with m.State("INSN_WAIT"):
-                if self.allow_overlap:
-                    stopping = dbg.stopping_o
-                else:
-                    stopping = Const(0)
+                # when using "single-step" mode, checking dbg.stopping_o
+                # prevents progress.  allow issue to proceed once started
+                stopping = Const(0)
+                #if self.allow_overlap:
+                #    stopping = dbg.stopping_o
                 with m.If(stopping):
                     # stopping: jump back to idle
                     m.next = "ISSUE_START"
@@ -1231,10 +1236,11 @@ class TestIssuerInternal(TestIssuerBase):
 
             # handshake with execution FSM, move to "wait" once acknowledged
             with m.State("INSN_EXECUTE"):
-                if self.allow_overlap:
-                    stopping = dbg.stopping_o
-                else:
-                    stopping = Const(0)
+                # when using "single-step" mode, checking dbg.stopping_o
+                # prevents progress.  allow execute to proceed once started
+                stopping = Const(0)
+                #if self.allow_overlap:
+                #    stopping = dbg.stopping_o
                 with m.If(stopping):
                     # stopping: jump back to idle
                     m.next = "ISSUE_START"