# 64-bit: bit 2 of pc decides which word to select
return f_instr_o.word_select(pc[2], 32)
+# gets state input or reads from state regfile
+def state_get(m, state_i, name, regfile, regnum):
+ comb = m.d.comb
+ sync = m.d.sync
+ # read the PC
+ res = Signal(64, reset_less=True, name=name)
+ res_ok_delay = Signal(name="%s_ok_delay" % name)
+ sync += res_ok_delay.eq(~state_i.ok)
+ with m.If(state_i.ok):
+ # incoming override (start from pc_i)
+ comb += res.eq(state_i.data)
+ with m.Else():
+ # otherwise read StateRegs regfile for PC...
+ comb += regfile.ren.eq(1<<regnum)
+ # ... but on a 1-clock delay
+ with m.If(res_ok_delay):
+ comb += res.eq(regfile.data_o)
+ return res
+
class TestIssuerInternal(Elaboratable):
"""TestIssuer - reads instructions from TestMemory and issues them
"""
def __init__(self, pspec):
+ # test is SVP64 is to be enabled
+ self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
+
# JTAG interface. add this right at the start because if it's
# added it *modifies* the pspec, by adding enable/disable signals
# for parts of the rest of the core
pdecode = create_pdecode()
self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
- opkls=IssuerDecode2ToOperand)
- self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
+ opkls=IssuerDecode2ToOperand,
+ svp64_en=self.svp64_en)
+ if self.svp64_en:
+ self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
# Test Instruction memory
self.imem = ConfigFetchUnit(pspec).fu
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
self.state_nia.wen.name = 'state_nia_wen'
- def fetch_fsm(self, m, core, pc, svstate, nia,
+ # pulse to synchronize the simulator at instruction end
+ self.insn_done = Signal()
+
+ if self.svp64_en:
+ # store copies of predicate masks
+ self.srcmask = Signal(64)
+ self.dstmask = Signal(64)
+
+ def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i):
"""fetch FSM
comb = m.d.comb
sync = m.d.sync
pdecode2 = self.pdecode2
- svp64 = self.svp64
cur_state = self.cur_state
dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
with m.Else():
# not busy: instruction fetched
insn = get_insn(self.imem.f_instr_o, cur_state.pc)
- # decode the SVP64 prefix, if any
- comb += svp64.raw_opcode_in.eq(insn)
- comb += svp64.bigendian.eq(self.core_bigendian_i)
- # pass the decoded prefix (if any) to PowerDecoder2
- sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
- # calculate the address of the following instruction
- insn_size = Mux(svp64.is_svp64_mode, 8, 4)
- sync += nia.eq(cur_state.pc + insn_size)
- with m.If(~svp64.is_svp64_mode):
- # with no prefix, store the instruction
- # and hand it directly to the next FSM
+ if self.svp64_en:
+ svp64 = self.svp64
+ # decode the SVP64 prefix, if any
+ comb += svp64.raw_opcode_in.eq(insn)
+ comb += svp64.bigendian.eq(self.core_bigendian_i)
+ # pass the decoded prefix (if any) to PowerDecoder2
+ sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
+ # remember whether this is a prefixed instruction, so
+ # the FSM can readily loop when VL==0
+ sync += is_svp64_mode.eq(svp64.is_svp64_mode)
+ # calculate the address of the following instruction
+ insn_size = Mux(svp64.is_svp64_mode, 8, 4)
+ sync += nia.eq(cur_state.pc + insn_size)
+ with m.If(~svp64.is_svp64_mode):
+ # with no prefix, store the instruction
+ # and hand it directly to the next FSM
+ sync += dec_opcode_i.eq(insn)
+ m.next = "INSN_READY"
+ with m.Else():
+ # fetch the rest of the instruction from memory
+ comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ m.next = "INSN_READ2"
+ else:
+ # not SVP64 - 32-bit only
+ sync += nia.eq(cur_state.pc + 4)
sync += dec_opcode_i.eq(insn)
m.next = "INSN_READY"
- with m.Else():
- # fetch the rest of the instruction from memory
- comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- m.next = "INSN_READ2"
with m.State("INSN_READ2"):
with m.If(self.imem.f_busy_o): # zzz...
insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
sync += dec_opcode_i.eq(insn)
m.next = "INSN_READY"
+ # TODO: probably can start looking at pdecode2.rm_dec
+ # here (or maybe even in INSN_READ state, if svp64_mode
+ # detected, in order to trigger - and wait for - the
+ # predicate reading.
with m.State("INSN_READY"):
# hand over the instruction, to be decoded
with m.If(fetch_insn_ready_i):
m.next = "IDLE"
+ def fetch_predicate_fsm(self, m, core, TODO):
+ """fetch_predicate_fsm - obtains (constructs in the case of CR)
+ src/dest predicate masks
+
+ https://bugs.libre-soc.org/show_bug.cgi?id=617
+ the predicates can be read here, by using IntRegs r_ports['pred']
+ or CRRegs r_ports['pred']. in the case of CRs it will have to
+ be done through multiple reads, extracting one relevant at a time.
+ later, a faster way would be to use the 32-bit-wide CR port but
+ this is more complex decoding, here. equivalent code used in
+ ISACaller is "from soc.decoder.isa.caller import get_predcr"
+ """
+ comb = m.d.comb
+ sync = m.d.sync
+ pdecode2 = self.pdecode2
+ rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
+ predmode = rm_dec.predmode
+ srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
+
def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
- dbg, core_rst,
+ dbg, core_rst, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i,
exec_insn_valid_i, exec_insn_ready_o,
with m.FSM(name="issue_fsm"):
- # go fetch the instruction at the current PC
+ # sync with the "fetch" phase which is reading the instruction
# at this point, there is no instruction running, that
# could inadvertently update the PC.
- with m.State("INSN_FETCH"):
+ with m.State("ISSUE_START"):
# wait on "core stop" release, before next fetch
# need to do this here, in case we are in a VL==0 loop
with m.If(~dbg.core_stop_o & ~core_rst):
- comb += fetch_pc_valid_i.eq(1)
- with m.If(fetch_pc_ready_o):
+ comb += fetch_pc_valid_i.eq(1) # tell fetch to start
+ with m.If(fetch_pc_ready_o): # fetch acknowledged us
m.next = "INSN_WAIT"
with m.Else():
+ # tell core it's stopped, and acknowledge debug handshake
comb += core.core_stopped_i.eq(1)
comb += dbg.core_stopped_i.eq(1)
# while stopped, allow updating the PC and SVSTATE
sync += core.state.eq(cur_state)
sync += core.raw_insn_i.eq(dec_opcode_i)
sync += core.bigendian_i.eq(self.core_bigendian_i)
- # loop into INSN_FETCH if it's a vector instruction
+ # set RA_OR_ZERO detection in satellite decoders
+ sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+ # loop into ISSUE_START if it's a SVP64 instruction
# and VL == 0. this because VL==0 is a for-loop
# from 0 to 0 i.e. always, always a NOP.
cur_vl = cur_state.svstate.vl
- with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
+ with m.If(is_svp64_mode & (cur_vl == 0)):
# update the PC before fetching the next instruction
# since we are in a VL==0 loop, no instruction was
# executed that we could be overwriting
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
comb += self.state_w_pc.data_i.eq(nia)
- m.next = "INSN_FETCH"
+ comb += self.insn_done.eq(1)
+ m.next = "ISSUE_START"
with m.Else():
m.next = "INSN_EXECUTE" # move to "execute"
+ # handshake with execution FSM, move to "wait" once acknowledged
with m.State("INSN_EXECUTE"):
- comb += exec_insn_valid_i.eq(1)
- with m.If(exec_insn_ready_o):
+ # with m.If(is_svp64_mode):
+ # TODO advance src/dst step to "skip" over predicated-out
+ # from self.srcmask and self.dstmask
+ # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
+ # but still without exceeding VL in either case
+ comb += exec_insn_valid_i.eq(1) # trigger execute
+ with m.If(exec_insn_ready_o): # execute acknowledged us
m.next = "EXECUTE_WAIT"
with m.State("EXECUTE_WAIT"):
with m.If(~dbg.core_stop_o & ~core_rst):
comb += exec_pc_ready_i.eq(1)
with m.If(exec_pc_valid_o):
- # precalculate srcstep+1
+ # precalculate srcstep+1 and dststep+1
next_srcstep = Signal.like(cur_state.svstate.srcstep)
+ next_dststep = Signal.like(cur_state.svstate.dststep)
comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
+ comb += next_dststep.eq(cur_state.svstate.dststep+1)
+
# was this the last loop iteration?
is_last = Signal()
cur_vl = cur_state.svstate.vl
# instruction, go directly back to Fetch, without
# updating either PC or SVSTATE
with m.If(pc_changed | sv_changed):
- m.next = "INSN_FETCH"
+ m.next = "ISSUE_START"
# also return to Fetch, when no output was a vector
# (regardless of SRCSTEP and VL), or when the last
# instruction was really the last one of the VL loop
- with m.Elif(pdecode2.no_out_vec | is_last):
+ with m.Elif((~pdecode2.loop_continue) | is_last):
# before going back to fetch, update the PC state
# register with the NIA.
# ok here we are not reading the branch unit.
comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
comb += self.state_w_pc.data_i.eq(nia)
# reset SRCSTEP before returning to Fetch
- with m.If(~pdecode2.no_out_vec):
+ with m.If(pdecode2.loop_continue):
comb += new_svstate.srcstep.eq(0)
+ comb += new_svstate.dststep.eq(0)
comb += update_svstate.eq(1)
- m.next = "INSN_FETCH"
+ m.next = "ISSUE_START"
# returning to Execute? then, first update SRCSTEP
with m.Else():
comb += new_svstate.srcstep.eq(next_srcstep)
+ comb += new_svstate.dststep.eq(next_dststep)
comb += update_svstate.eq(1)
m.next = "DECODE_SV"
sync += core.e.eq(pdecode2.e)
sync += core.state.eq(cur_state)
sync += core.bigendian_i.eq(self.core_bigendian_i)
+ sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
m.next = "INSN_EXECUTE" # move to "execute"
# check if svstate needs updating: if so, write it to State Regfile
comb = m.d.comb
sync = m.d.sync
pdecode2 = self.pdecode2
- svp64 = self.svp64
# temporaries
core_busy_o = core.busy_o # core is busy
with m.If(~core_busy_o): # instruction done!
comb += exec_pc_valid_o.eq(1)
with m.If(exec_pc_ready_i):
+ comb += self.insn_done.eq(1)
m.next = "INSN_START" # back to fetch
def elaborate(self, platform):
# instruction decoder
pdecode = create_pdecode()
m.submodules.dec2 = pdecode2 = self.pdecode2
- m.submodules.svp64 = svp64 = self.svp64
+ if self.svp64_en:
+ m.submodules.svp64 = svp64 = self.svp64
# convenience
dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
pc_changed = Signal() # note write to PC
sv_changed = Signal() # note write to SVSTATE
- # read the PC
- pc = Signal(64, reset_less=True)
- pc_ok_delay = Signal()
- sync += pc_ok_delay.eq(~self.pc_i.ok)
- with m.If(self.pc_i.ok):
- # incoming override (start from pc_i)
- comb += pc.eq(self.pc_i.data)
- with m.Else():
- # otherwise read StateRegs regfile for PC...
- comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
- # ... but on a 1-clock delay
- with m.If(pc_ok_delay):
- comb += pc.eq(self.state_r_pc.data_o)
-
- # read svstate
- svstate = Signal(64, reset_less=True)
- svstate_ok_delay = Signal()
- sync += svstate_ok_delay.eq(~self.svstate_i.ok)
- with m.If(self.svstate_i.ok):
- # incoming override (start from svstate__i)
- comb += svstate.eq(self.svstate_i.data)
- with m.Else():
- # otherwise read StateRegs regfile for SVSTATE...
- comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
- # ... but on a 1-clock delay
- with m.If(svstate_ok_delay):
- comb += svstate.eq(self.state_r_sv.data_o)
+ # read state either from incoming override or from regfile
+ # TODO: really should be doing MSR in the same say
+ pc = state_get(m, self.pc_i, "pc", # read PC
+ self.state_r_pc, StateRegs.PC)
+ svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
+ self.state_r_sv, StateRegs.SVSTATE)
# don't write pc every cycle
comb += self.state_w_pc.wen.eq(0)
comb += dbg.state.svstate.eq(svstate)
comb += dbg.state.msr.eq(cur_state.msr)
+ # pass the prefix mode from Fetch to Issue, so the latter can loop
+ # on VL==0
+ is_svp64_mode = Signal()
+
# there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
# these are the handshake signals between fetch and decode/execute
# lives. the ready/valid signalling is used to communicate between
# the three.
- self.fetch_fsm(m, core, pc, svstate, nia,
+ self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i)
self.issue_fsm(m, core, pc_changed, sv_changed, nia,
- dbg, core_rst,
+ dbg, core_rst, is_svp64_mode,
fetch_pc_ready_o, fetch_pc_valid_i,
fetch_insn_valid_o, fetch_insn_ready_i,
exec_insn_valid_i, exec_insn_ready_o,
projects / soc.git / blobdiff