"""
from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
- ClockDomain, DomainRenamer, Mux)
+ ClockDomain, DomainRenamer, Mux, Const)
from nmigen.cli import rtlil
from nmigen.cli import main
import sys
from soc.config.state import CoreState
from soc.interrupts.xics import XICS_ICP, XICS_ICS
from soc.bus.simple_gpio import SimpleGPIO
+from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
from soc.clock.select import ClockSelect
from soc.clock.dummypll import DummyPLL
+from soc.sv.svstate import SVSTATERec
from nmutil.util import rising_edge
# 64-bit: bit 2 of pc decides which word to select
return f_instr_o.word_select(pc[2], 32)
+# gets state input or reads from state regfile
+def state_get(m, state_i, name, regfile, regnum):
+ comb = m.d.comb
+ sync = m.d.sync
+ # read the PC
+ res = Signal(64, reset_less=True, name=name)
+ res_ok_delay = Signal(name="%s_ok_delay" % name)
+ sync += res_ok_delay.eq(~state_i.ok)
+ with m.If(state_i.ok):
+ # incoming override (start from pc_i)
+ comb += res.eq(state_i.data)
+ with m.Else():
+ # otherwise read StateRegs regfile for PC...
+ comb += regfile.ren.eq(1<<regnum)
+ # ... but on a 1-clock delay
+ with m.If(res_ok_delay):
+ comb += res.eq(regfile.data_o)
+ return res
+
class TestIssuerInternal(Elaboratable):
"""TestIssuer - reads instructions from TestMemory and issues them
"""
def __init__(self, pspec):
+ # test is SVP64 is to be enabled
+ self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
+
# JTAG interface. add this right at the start because if it's
# added it *modifies* the pspec, by adding enable/disable signals
# for parts of the rest of the core
# honestly probably not.
pspec.wb_icache_en = self.jtag.wb_icache_en
pspec.wb_dcache_en = self.jtag.wb_dcache_en
+ self.wb_sram_en = self.jtag.wb_sram_en
+ else:
+ self.wb_sram_en = Const(1)
+
+ # add 4k sram blocks?
+ self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
+ pspec.sram4x4kblock == True)
+ if self.sram4x4k:
+ self.sram4k = []
+ for i in range(4):
+ self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
+ features={'err'}))
# add interrupt controller?
self.xics = hasattr(pspec, "xics") and pspec.xics == True
# instruction decoder. goes into Trap Record
pdecode = create_pdecode()
- self.cur_state = CoreState("cur") # current state (MSR/PC/EINT)
+ self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
- opkls=IssuerDecode2ToOperand)
- self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
+ opkls=IssuerDecode2ToOperand,
+ svp64_en=self.svp64_en)
+ if self.svp64_en:
+ self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
# Test Instruction memory
self.imem = ConfigFetchUnit(pspec).fu
# instruction go/monitor
self.pc_o = Signal(64, reset_less=True)
self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
+ self.svstate_i = Data(32, "svstate_i") # ditto
self.core_bigendian_i = Signal()
self.busy_o = Signal(reset_less=True)
self.memerr_o = Signal(reset_less=True)
- # FAST regfile read /write ports for PC, MSR, DEC/TB
+ # STATE regfile read /write ports for PC, MSR, SVSTATE
staterf = self.core.regs.rf['state']
self.state_r_pc = staterf.r_ports['cia'] # PC rd
self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
self.state_r_msr = staterf.r_ports['msr'] # MSR rd
+ self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
+ self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
# DMI interface access
intrf = self.core.regs.rf['int']
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
self.state_nia.wen.name = 'state_nia_wen'
+ # pulse to synchronize the simulator at instruction end
+ self.insn_done = Signal()
+
+ if self.svp64_en:
+ # store copies of predicate masks
+ self.srcmask = Signal(64)
+ self.dstmask = Signal(64)
+
+ def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
+ fetch_pc_ready_o, fetch_pc_valid_i,
+ fetch_insn_valid_o, fetch_insn_ready_i):
+ """fetch FSM
+ this FSM performs fetch of raw instruction data, partial-decodes
+ it 32-bit at a time to detect SVP64 prefixes, and will optionally
+ read a 2nd 32-bit quantity if that occurs.
+ """
+ comb = m.d.comb
+ sync = m.d.sync
+ pdecode2 = self.pdecode2
+ cur_state = self.cur_state
+ dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+
+ msr_read = Signal(reset=1)
+
+ with m.FSM(name='fetch_fsm'):
+
+ # waiting (zzz)
+ with m.State("IDLE"):
+ comb += fetch_pc_ready_o.eq(1)
+ with m.If(fetch_pc_valid_i):
+ # instruction allowed to go: start by reading the PC
+ # capture the PC and also drop it into Insn Memory
+ # we have joined a pair of combinatorial memory
+ # lookups together. this is Generally Bad.
+ comb += self.imem.a_pc_i.eq(pc)
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ sync += cur_state.pc.eq(pc)
+ sync += cur_state.svstate.eq(svstate) # and svstate
+
+ # initiate read of MSR. arrives one clock later
+ comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
+ sync += msr_read.eq(0)
+
+ m.next = "INSN_READ" # move to "wait for bus" phase
+
+ # dummy pause to find out why simulation is not keeping up
+ with m.State("INSN_READ"):
+ # one cycle later, msr/sv read arrives. valid only once.
+ with m.If(~msr_read):
+ sync += msr_read.eq(1) # yeah don't read it again
+ sync += cur_state.msr.eq(self.state_r_msr.data_o)
+ with m.If(self.imem.f_busy_o): # zzz...
+ # busy: stay in wait-read
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ with m.Else():
+ # not busy: instruction fetched
+ insn = get_insn(self.imem.f_instr_o, cur_state.pc)
+ if self.svp64_en:
+ svp64 = self.svp64
+ # decode the SVP64 prefix, if any
+ comb += svp64.raw_opcode_in.eq(insn)
+ comb += svp64.bigendian.eq(self.core_bigendian_i)
+ # pass the decoded prefix (if any) to PowerDecoder2
+ sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
+ # remember whether this is a prefixed instruction, so
+ # the FSM can readily loop when VL==0
+ sync += is_svp64_mode.eq(svp64.is_svp64_mode)
+ # calculate the address of the following instruction
+ insn_size = Mux(svp64.is_svp64_mode, 8, 4)
+ sync += nia.eq(cur_state.pc + insn_size)
+ with m.If(~svp64.is_svp64_mode):
+ # with no prefix, store the instruction
+ # and hand it directly to the next FSM
+ sync += dec_opcode_i.eq(insn)
+ m.next = "INSN_READY"
+ with m.Else():
+ # fetch the rest of the instruction from memory
+ comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ m.next = "INSN_READ2"
+ else:
+ # not SVP64 - 32-bit only
+ sync += nia.eq(cur_state.pc + 4)
+ sync += dec_opcode_i.eq(insn)
+ m.next = "INSN_READY"
+
+ with m.State("INSN_READ2"):
+ with m.If(self.imem.f_busy_o): # zzz...
+ # busy: stay in wait-read
+ comb += self.imem.a_valid_i.eq(1)
+ comb += self.imem.f_valid_i.eq(1)
+ with m.Else():
+ # not busy: instruction fetched
+ insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
+ sync += dec_opcode_i.eq(insn)
+ m.next = "INSN_READY"
+ # TODO: probably can start looking at pdecode2.rm_dec
+ # here (or maybe even in INSN_READ state, if svp64_mode
+ # detected, in order to trigger - and wait for - the
+ # predicate reading.
+
+ with m.State("INSN_READY"):
+ # hand over the instruction, to be decoded
+ comb += fetch_insn_valid_o.eq(1)
+ with m.If(fetch_insn_ready_i):
+ m.next = "IDLE"
+
+ def fetch_predicate_fsm(self, m, core, TODO):
+ """fetch_predicate_fsm - obtains (constructs in the case of CR)
+ src/dest predicate masks
+
+ https://bugs.libre-soc.org/show_bug.cgi?id=617
+ the predicates can be read here, by using IntRegs r_ports['pred']
+ or CRRegs r_ports['pred']. in the case of CRs it will have to
+ be done through multiple reads, extracting one relevant at a time.
+ later, a faster way would be to use the 32-bit-wide CR port but
+ this is more complex decoding, here. equivalent code used in
+ ISACaller is "from soc.decoder.isa.caller import get_predcr"
+ """
+ comb = m.d.comb
+ sync = m.d.sync
+ pdecode2 = self.pdecode2
+ rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
+ predmode = rm_dec.predmode
+ srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
+
+ def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
+ dbg, core_rst, is_svp64_mode,
+ fetch_pc_ready_o, fetch_pc_valid_i,
+ fetch_insn_valid_o, fetch_insn_ready_i,
+ exec_insn_valid_i, exec_insn_ready_o,
+ exec_pc_valid_o, exec_pc_ready_i):
+ """issue FSM
+
+ decode / issue FSM. this interacts with the "fetch" FSM
+ through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
+ (outgoing). also interacts with the "execute" FSM
+ through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
+ (incoming).
+ SVP64 RM prefixes have already been set up by the
+ "fetch" phase, so execute is fairly straightforward.
+ """
+
+ comb = m.d.comb
+ sync = m.d.sync
+ pdecode2 = self.pdecode2
+ cur_state = self.cur_state
+
+ # temporaries
+ dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+
+ # for updating svstate (things like srcstep etc.)
+ update_svstate = Signal() # set this (below) if updating
+ new_svstate = SVSTATERec("new_svstate")
+ comb += new_svstate.eq(cur_state.svstate)
+
+ with m.FSM(name="issue_fsm"):
+
+ # sync with the "fetch" phase which is reading the instruction
+ # at this point, there is no instruction running, that
+ # could inadvertently update the PC.
+ with m.State("ISSUE_START"):
+ # wait on "core stop" release, before next fetch
+ # need to do this here, in case we are in a VL==0 loop
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ comb += fetch_pc_valid_i.eq(1) # tell fetch to start
+ with m.If(fetch_pc_ready_o): # fetch acknowledged us
+ m.next = "INSN_WAIT"
+ with m.Else():
+ # tell core it's stopped, and acknowledge debug handshake
+ comb += core.core_stopped_i.eq(1)
+ comb += dbg.core_stopped_i.eq(1)
+ # while stopped, allow updating the PC and SVSTATE
+ with m.If(self.pc_i.ok):
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+ sync += pc_changed.eq(1)
+ with m.If(self.svstate_i.ok):
+ comb += new_svstate.eq(self.svstate_i.data)
+ comb += update_svstate.eq(1)
+ sync += sv_changed.eq(1)
+
+ # decode the instruction when it arrives
+ with m.State("INSN_WAIT"):
+ comb += fetch_insn_ready_i.eq(1)
+ with m.If(fetch_insn_valid_o):
+ # decode the instruction
+ sync += core.e.eq(pdecode2.e)
+ sync += core.state.eq(cur_state)
+ sync += core.raw_insn_i.eq(dec_opcode_i)
+ sync += core.bigendian_i.eq(self.core_bigendian_i)
+ # set RA_OR_ZERO detection in satellite decoders
+ sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+ # loop into ISSUE_START if it's a SVP64 instruction
+ # and VL == 0. this because VL==0 is a for-loop
+ # from 0 to 0 i.e. always, always a NOP.
+ cur_vl = cur_state.svstate.vl
+ with m.If(is_svp64_mode & (cur_vl == 0)):
+ # update the PC before fetching the next instruction
+ # since we are in a VL==0 loop, no instruction was
+ # executed that we could be overwriting
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(nia)
+ comb += self.insn_done.eq(1)
+ m.next = "ISSUE_START"
+ with m.Else():
+ m.next = "INSN_EXECUTE" # move to "execute"
+
+ # handshake with execution FSM, move to "wait" once acknowledged
+ with m.State("INSN_EXECUTE"):
+ # with m.If(is_svp64_mode):
+ # TODO advance src/dst step to "skip" over predicated-out
+ # from self.srcmask and self.dstmask
+ # https://bugs.libre-soc.org/show_bug.cgi?id=617#c3
+ # but still without exceeding VL in either case
+ comb += exec_insn_valid_i.eq(1) # trigger execute
+ with m.If(exec_insn_ready_o): # execute acknowledged us
+ m.next = "EXECUTE_WAIT"
+
+ with m.State("EXECUTE_WAIT"):
+ # wait on "core stop" release, at instruction end
+ # need to do this here, in case we are in a VL>1 loop
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ comb += exec_pc_ready_i.eq(1)
+ with m.If(exec_pc_valid_o):
+ # precalculate srcstep+1 and dststep+1
+ next_srcstep = Signal.like(cur_state.svstate.srcstep)
+ next_dststep = Signal.like(cur_state.svstate.dststep)
+ comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
+ comb += next_dststep.eq(cur_state.svstate.dststep+1)
+
+ # was this the last loop iteration?
+ is_last = Signal()
+ cur_vl = cur_state.svstate.vl
+ comb += is_last.eq(next_srcstep == cur_vl)
+
+ # if either PC or SVSTATE were changed by the previous
+ # instruction, go directly back to Fetch, without
+ # updating either PC or SVSTATE
+ with m.If(pc_changed | sv_changed):
+ m.next = "ISSUE_START"
+
+ # also return to Fetch, when no output was a vector
+ # (regardless of SRCSTEP and VL), or when the last
+ # instruction was really the last one of the VL loop
+ with m.Elif((~pdecode2.loop_continue) | is_last):
+ # before going back to fetch, update the PC state
+ # register with the NIA.
+ # ok here we are not reading the branch unit.
+ # TODO: this just blithely overwrites whatever
+ # pipeline updated the PC
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(nia)
+ # reset SRCSTEP before returning to Fetch
+ with m.If(pdecode2.loop_continue):
+ comb += new_svstate.srcstep.eq(0)
+ comb += new_svstate.dststep.eq(0)
+ comb += update_svstate.eq(1)
+ m.next = "ISSUE_START"
+
+ # returning to Execute? then, first update SRCSTEP
+ with m.Else():
+ comb += new_svstate.srcstep.eq(next_srcstep)
+ comb += new_svstate.dststep.eq(next_dststep)
+ comb += update_svstate.eq(1)
+ m.next = "DECODE_SV"
+
+ with m.Else():
+ comb += core.core_stopped_i.eq(1)
+ comb += dbg.core_stopped_i.eq(1)
+ # while stopped, allow updating the PC and SVSTATE
+ with m.If(self.pc_i.ok):
+ comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+ comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+ sync += pc_changed.eq(1)
+ with m.If(self.svstate_i.ok):
+ comb += new_svstate.eq(self.svstate_i.data)
+ comb += update_svstate.eq(1)
+ sync += sv_changed.eq(1)
+
+ # need to decode the instruction again, after updating SRCSTEP
+ # in the previous state.
+ # mostly a copy of INSN_WAIT, but without the actual wait
+ with m.State("DECODE_SV"):
+ # decode the instruction
+ sync += core.e.eq(pdecode2.e)
+ sync += core.state.eq(cur_state)
+ sync += core.bigendian_i.eq(self.core_bigendian_i)
+ sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
+ m.next = "INSN_EXECUTE" # move to "execute"
+
+ # check if svstate needs updating: if so, write it to State Regfile
+ with m.If(update_svstate):
+ comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
+ comb += self.state_w_sv.data_i.eq(new_svstate)
+ sync += cur_state.svstate.eq(new_svstate) # for next clock
+
+ def execute_fsm(self, m, core, pc_changed, sv_changed,
+ exec_insn_valid_i, exec_insn_ready_o,
+ exec_pc_valid_o, exec_pc_ready_i):
+ """execute FSM
+
+ execute FSM. this interacts with the "issue" FSM
+ through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
+ (outgoing). SVP64 RM prefixes have already been set up by the
+ "issue" phase, so execute is fairly straightforward.
+ """
+
+ comb = m.d.comb
+ sync = m.d.sync
+ pdecode2 = self.pdecode2
+
+ # temporaries
+ core_busy_o = core.busy_o # core is busy
+ core_ivalid_i = core.ivalid_i # instruction is valid
+ core_issue_i = core.issue_i # instruction is issued
+ insn_type = core.e.do.insn_type # instruction MicroOp type
+
+ with m.FSM(name="exec_fsm"):
+
+ # waiting for instruction bus (stays there until not busy)
+ with m.State("INSN_START"):
+ comb += exec_insn_ready_o.eq(1)
+ with m.If(exec_insn_valid_i):
+ comb += core_ivalid_i.eq(1) # instruction is valid
+ comb += core_issue_i.eq(1) # and issued
+ sync += sv_changed.eq(0)
+ sync += pc_changed.eq(0)
+ m.next = "INSN_ACTIVE" # move to "wait completion"
+
+ # instruction started: must wait till it finishes
+ with m.State("INSN_ACTIVE"):
+ with m.If(insn_type != MicrOp.OP_NOP):
+ comb += core_ivalid_i.eq(1) # instruction is valid
+ # note changes to PC and SVSTATE
+ with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
+ sync += sv_changed.eq(1)
+ with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
+ sync += pc_changed.eq(1)
+ with m.If(~core_busy_o): # instruction done!
+ comb += exec_pc_valid_o.eq(1)
+ with m.If(exec_pc_ready_i):
+ comb += self.insn_done.eq(1)
+ m.next = "INSN_START" # back to fetch
+
def elaborate(self, platform):
m = Module()
comb, sync = m.d.comb, m.d.sync
cur_state = self.cur_state
+ # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
+ if self.sram4x4k:
+ for i, sram in enumerate(self.sram4k):
+ m.submodules["sram4k_%d" % i] = sram
+ comb += sram.enable.eq(self.wb_sram_en)
+
# XICS interrupt handler
if self.xics:
m.submodules.xics_icp = icp = self.xics_icp
# instruction decoder
pdecode = create_pdecode()
m.submodules.dec2 = pdecode2 = self.pdecode2
- m.submodules.svp64 = svp64 = self.svp64
+ if self.svp64_en:
+ m.submodules.svp64 = svp64 = self.svp64
# convenience
dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
# PC and instruction from I-Memory
- pc_changed = Signal() # note write to PC
comb += self.pc_o.eq(cur_state.pc)
- ilatch = Signal(32)
-
- # address of the next instruction, in the absence of a branch
- # depends on the instruction size
- nia = Signal(64, reset_less=True)
+ pc_changed = Signal() # note write to PC
+ sv_changed = Signal() # note write to SVSTATE
- # read the PC
- pc = Signal(64, reset_less=True)
- pc_ok_delay = Signal()
- sync += pc_ok_delay.eq(~self.pc_i.ok)
- with m.If(self.pc_i.ok):
- # incoming override (start from pc_i)
- comb += pc.eq(self.pc_i.data)
- with m.Else():
- # otherwise read StateRegs regfile for PC...
- comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
- # ... but on a 1-clock delay
- with m.If(pc_ok_delay):
- comb += pc.eq(self.state_r_pc.data_o)
+ # read state either from incoming override or from regfile
+ # TODO: really should be doing MSR in the same say
+ pc = state_get(m, self.pc_i, "pc", # read PC
+ self.state_r_pc, StateRegs.PC)
+ svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
+ self.state_r_sv, StateRegs.SVSTATE)
# don't write pc every cycle
comb += self.state_w_pc.wen.eq(0)
# don't read msr every cycle
comb += self.state_r_msr.ren.eq(0)
- msr_read = Signal(reset=1)
+
+ # address of the next instruction, in the absence of a branch
+ # depends on the instruction size
+ nia = Signal(64, reset_less=True)
# connect up debug signals
# TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
comb += dbg.terminate_i.eq(core.core_terminate_o)
comb += dbg.state.pc.eq(pc)
- #comb += dbg.state.pc.eq(cur_state.pc)
+ comb += dbg.state.svstate.eq(svstate)
comb += dbg.state.msr.eq(cur_state.msr)
- # temporaries
- core_busy_o = core.busy_o # core is busy
- core_ivalid_i = core.ivalid_i # instruction is valid
- core_issue_i = core.issue_i # instruction is issued
- dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
+ # pass the prefix mode from Fetch to Issue, so the latter can loop
+ # on VL==0
+ is_svp64_mode = Signal()
- insn_type = core.e.do.insn_type
+ # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
+ # these are the handshake signals between fetch and decode/execute
- # handshake signals between fetch and decode/execute
# fetch FSM can run as soon as the PC is valid
- fetch_pc_valid_i = Signal()
- fetch_pc_ready_o = Signal()
- # when done, deliver the instruction to the next FSM
- fetch_insn_o = Signal(32, reset_less=True)
+ fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
+ fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
+
+ # fetch FSM hands over the instruction to be decoded / issued
fetch_insn_valid_o = Signal()
fetch_insn_ready_i = Signal()
- # actually use a nmigen FSM for the first time (w00t)
- # this FSM is perhaps unusual in that it detects conditions
- # then "holds" information, combinatorially, for the core
+ # issue FSM delivers the instruction to the be executed
+ exec_insn_valid_i = Signal()
+ exec_insn_ready_o = Signal()
+
+ # execute FSM, hands over the PC/SVSTATE back to the issue FSM
+ exec_pc_valid_o = Signal()
+ exec_pc_ready_i = Signal()
+
+ # the FSMs here are perhaps unusual in that they detect conditions
+ # then "hold" information, combinatorially, for the core
# (as opposed to using sync - which would be on a clock's delay)
# this includes the actual opcode, valid flags and so on.
- with m.FSM(name='fetch_fsm'):
- # waiting (zzz)
- with m.State("IDLE"):
- with m.If(~dbg.core_stop_o & ~core_rst):
- comb += fetch_pc_ready_o.eq(1)
- with m.If(fetch_pc_valid_i):
- # instruction allowed to go: start by reading the PC
- # capture the PC and also drop it into Insn Memory
- # we have joined a pair of combinatorial memory
- # lookups together. this is Generally Bad.
- comb += self.imem.a_pc_i.eq(pc)
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- sync += cur_state.pc.eq(pc)
-
- # initiate read of MSR. arrives one clock later
- comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
- sync += msr_read.eq(0)
-
- m.next = "INSN_READ" # move to "wait for bus" phase
- with m.Else():
- comb += core.core_stopped_i.eq(1)
- comb += dbg.core_stopped_i.eq(1)
+ # Fetch, then Issue, then Execute. Issue is where the VL for-loop
+ # lives. the ready/valid signalling is used to communicate between
+ # the three.
- # dummy pause to find out why simulation is not keeping up
- with m.State("INSN_READ"):
- # one cycle later, msr read arrives. valid only once.
- with m.If(~msr_read):
- sync += msr_read.eq(1) # yeah don't read it again
- sync += cur_state.msr.eq(self.state_r_msr.data_o)
- with m.If(self.imem.f_busy_o): # zzz...
- # busy: stay in wait-read
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- with m.Else():
- # not busy: instruction fetched
- insn = get_insn(self.imem.f_instr_o, cur_state.pc)
- # decode the SVP64 prefix, if any
- comb += svp64.raw_opcode_in.eq(insn)
- comb += svp64.bigendian.eq(self.core_bigendian_i)
- # pass the decoded prefix (if any) to PowerDecoder2
- sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
- # calculate the address of the following instruction
- insn_size = Mux(svp64.is_svp64_mode, 8, 4)
- sync += nia.eq(cur_state.pc + insn_size)
- with m.If(~svp64.is_svp64_mode):
- # with no prefix, store the instruction
- # and hand it directly to the next FSM
- sync += fetch_insn_o.eq(insn)
- m.next = "INSN_READY"
- with m.Else():
- # fetch the rest of the instruction from memory
- comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- m.next = "INSN_READ2"
+ self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
+ fetch_pc_ready_o, fetch_pc_valid_i,
+ fetch_insn_valid_o, fetch_insn_ready_i)
- with m.State("INSN_READ2"):
- with m.If(self.imem.f_busy_o): # zzz...
- # busy: stay in wait-read
- comb += self.imem.a_valid_i.eq(1)
- comb += self.imem.f_valid_i.eq(1)
- with m.Else():
- # not busy: instruction fetched
- insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
- sync += fetch_insn_o.eq(insn)
- m.next = "INSN_READY"
-
- with m.State("INSN_READY"):
- # hand over the instruction, to be decoded
- comb += fetch_insn_valid_o.eq(1)
- with m.If(fetch_insn_ready_i):
- m.next = "IDLE"
+ self.issue_fsm(m, core, pc_changed, sv_changed, nia,
+ dbg, core_rst, is_svp64_mode,
+ fetch_pc_ready_o, fetch_pc_valid_i,
+ fetch_insn_valid_o, fetch_insn_ready_i,
+ exec_insn_valid_i, exec_insn_ready_o,
+ exec_pc_valid_o, exec_pc_ready_i)
- # decode / issue / execute FSM
- with m.FSM():
+ self.execute_fsm(m, core, pc_changed, sv_changed,
+ exec_insn_valid_i, exec_insn_ready_o,
+ exec_pc_valid_o, exec_pc_ready_i)
- # go fetch the instruction at the current PC
- # at this point, there is no instruction running, that
- # could inadvertently update the PC.
- with m.State("INSN_FETCH"):
- comb += fetch_pc_valid_i.eq(1)
- with m.If(fetch_pc_ready_o):
- m.next = "INSN_WAIT"
-
- # decode the instruction when it arrives
- with m.State("INSN_WAIT"):
- comb += fetch_insn_ready_i.eq(1)
- with m.If(fetch_insn_valid_o):
- # decode the instruction
- # TODO, before issuing new instruction first
- # check if it's SVP64. (svp64.is_svp64_mode set)
- # if yes, record the svp64_rm, put that into
- # pdecode2.sv_rm, then read another 32 bits (INSN_FETCH2?)
- comb += dec_opcode_i.eq(fetch_insn_o) # actual opcode
- sync += core.e.eq(pdecode2.e)
- sync += core.state.eq(cur_state)
- sync += core.raw_insn_i.eq(dec_opcode_i)
- sync += core.bigendian_i.eq(self.core_bigendian_i)
- sync += ilatch.eq(insn) # latch current insn
- # also drop PC and MSR into decode "state"
- m.next = "INSN_START" # move to "start"
+ # this bit doesn't have to be in the FSM: connect up to read
+ # regfiles on demand from DMI
+ self.do_dmi(m, dbg)
- # waiting for instruction bus (stays there until not busy)
- with m.State("INSN_START"):
- comb += core_ivalid_i.eq(1) # instruction is valid
- comb += core_issue_i.eq(1) # and issued
- sync += pc_changed.eq(0)
+ # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
+ # (which uses that in PowerDecoder2 to raise 0x900 exception)
+ self.tb_dec_fsm(m, cur_state.dec)
- m.next = "INSN_ACTIVE" # move to "wait completion"
+ return m
- # instruction started: must wait till it finishes
- with m.State("INSN_ACTIVE"):
- with m.If(insn_type != MicrOp.OP_NOP):
- comb += core_ivalid_i.eq(1) # instruction is valid
- with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
- sync += pc_changed.eq(1)
- with m.If(~core_busy_o): # instruction done!
- # ok here we are not reading the branch unit. TODO
- # this just blithely overwrites whatever pipeline
- # updated the PC
- with m.If(~pc_changed):
- comb += self.state_w_pc.wen.eq(1<<StateRegs.PC)
- comb += self.state_w_pc.data_i.eq(nia)
- sync += core.e.eq(0)
- sync += core.raw_insn_i.eq(0)
- sync += core.bigendian_i.eq(0)
- m.next = "INSN_FETCH" # back to fetch
+ def do_dmi(self, m, dbg):
+ comb = m.d.comb
+ sync = m.d.sync
+ dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
+ intrf = self.core.regs.rf['int']
- # this bit doesn't have to be in the FSM: connect up to read
- # regfiles on demand from DMI
with m.If(d_reg.req): # request for regfile access being made
# TODO: error-check this
# XXX should this be combinatorial? sync better?
comb += d_xer.data.eq(self.xer_r.data_o)
comb += d_xer.ack.eq(1)
- # DEC and TB inc/dec FSM
- self.tb_dec_fsm(m, cur_state.dec)
-
- return m
-
def tb_dec_fsm(self, m, spr_dec):
"""tb_dec_fsm
ports += list(self.imem.ibus.fields.values())
ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
+ if self.sram4x4k:
+ for sram in self.sram4k:
+ ports += list(sram.bus.fields.values())
+
if self.xics:
ports += list(self.xics_icp.bus.fields.values())
ports += list(self.xics_ics.bus.fields.values())
projects / soc.git / blobdiff