make PortInterface modules consistent with same API

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index e41bc65248c4030bdf80c1b0e079d56f2cb60f5a..b211a3630f8507cbfdd65c840f9e58e78ba38925 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -30,9 +30,9 @@ class TestIssuer(Elaboratable):
 
     efficiency and speed is not the main goal here: functional correctness is.
     """
-    def __init__(self, addrwid=6, idepth=6):
+    def __init__(self, addrwid=6, idepth=6, ifacetype='testpi'):
         # main instruction core
-        self.core = core = NonProductionCore(addrwid)
+        self.core = core = NonProductionCore(addrwid, ifacetype=ifacetype)
 
         # Test Instruction memory
         self.imem = TestMemory(32, idepth)