delay go_st by one cycle, break combinatorial loop

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 3d168da674490010dd2ead87d30f3f1456f6ab6c..cfc0be4850d1495e2e7673f95281bb46dc9a6b40 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -106,7 +106,7 @@ class TestIssuer(Elaboratable):
         l0 = core.l0
         ldst = core.fus.fus['ldst0']
         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
-        m.d.comb += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
+        m.d.sync += ldst.st.go_i.eq(ldst.st.rel_o) # link store-go direct to rel
 
         # PC and instruction from I-Memory
         current_insn = Signal(32) # current fetched instruction (note sync)
@@ -260,6 +260,7 @@ class TestIssuer(Elaboratable):
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
              'spr': 1,
+             'div': 1,
              'mul': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',